[PATCH v2 0/5] aarch64: Further CMPBR fixes
Karl Meakin via Sourceware Forge
forge-bot@forge-test.rdfm.org
Fri Oct 17 15:17:58 GMT 2025
Hi gcc-patches mailing list,
Karl Meakin <karmea01@sourceware.org> has requested that the following forgejo pull request
be published on the mailing list.
Created on: 2025-09-30 16:40:31+00:00
Latest update: 2025-10-17 15:17:28+00:00
Changes: 4 changed files, 46 additions, 59 deletions
Head revision: karmea01/gcc-TEST ref km/cmpbr-fix/v1 commit 762baaa6470d9ef71fd83f213b23e4c54677ba85
Base revision: gcc/gcc-TEST ref trunk commit dfb7e97dd214f7d8ca0fa970d81ad5ba805aaa8d r16-4456-gdfb7e97dd214f7
Merge base: dfb7e97dd214f7d8ca0fa970d81ad5ba805aaa8d
Full diff url: https://forge.sourceware.org/gcc/gcc-TEST/pulls/88.diff
Discussion: https://forge.sourceware.org/gcc/gcc-TEST/pulls/88
Requested Reviewers:
Fix an ICE when compiling code that does a movcc with floating point arguments
with `+cmpbr`. The fix was the same as bc11cbff9e648fdda2798bfa2d7151d5cd164b87,
so in the second commit I merged the two patterns.
Testing done:
`make check-gcc` and `make check-target` pass.
ChangeLog:
* v1: Initial series.
* v2: Move checks from the pattern body into the predicate, and remove unsued pattern
Changed files:
- A: gcc/testsuite/gcc.target/aarch64/cmpbr-4.c
- M: gcc/config/aarch64/aarch64.md
- M: gcc/config/aarch64/iterators.md
- M: gcc/config/aarch64/predicates.md
Karl Meakin (5):
aarch64: Fix condition accepted by mov<GPF>cc
aarch64: Merge mov<ALLI>cc with mov<GPF>cc
aarch64: Remove redundant checks
aarch64: Add `aarch64_comparison_operator_cc`
aarch64: Remove unused pattern
gcc/config/aarch64/aarch64.md | 74 +++++-----------------
gcc/config/aarch64/iterators.md | 4 ++
gcc/config/aarch64/predicates.md | 15 +++++
gcc/testsuite/gcc.target/aarch64/cmpbr-4.c | 12 ++++
4 files changed, 46 insertions(+), 59 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/cmpbr-4.c
Range-diff against v1:
1: 857e5eca8e1e ! 1: 852b3102e0da aarch64: Fix condition accepted by mov<GPF>cc
@@ gcc/config/aarch64/aarch64.md
}
)
+@@
+ (match_operand:GPF 3 "register_operand")))]
+ ""
+ {
+- rtx ccreg;
+ enum rtx_code code = GET_CODE (operands[1]);
+-
+ if (code == UNEQ || code == LTGT)
+ FAIL;
+
+- ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
+- XEXP (operands[1], 1));
+- operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
++ rtx ccreg = XEXP (operands[1], 0);
++ enum machine_mode ccmode = GET_MODE (ccreg);
++ if (GET_MODE_CLASS (ccmode) == MODE_CC)
++ gcc_assert (XEXP (operands[1], 1) == const0_rtx);
++ else if (ccmode == QImode || ccmode == HImode)
++ FAIL;
++ else
++ {
++ ccreg = aarch64_gen_compare_reg (code, ccreg, XEXP (operands[1], 1));
++ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
++ }
+ }
+ )
+
+@@
+ (match_operand:GPI 3 "register_operand")))]
+ ""
+ {
+- rtx ccreg;
+ enum rtx_code code = GET_CODE (operands[1]);
+-
+ if (code == UNEQ || code == LTGT)
+ FAIL;
+
+- ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
+- XEXP (operands[1], 1));
+- operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
++ rtx ccreg = XEXP (operands[1], 0);
++ enum machine_mode ccmode = GET_MODE (ccreg);
++ if (GET_MODE_CLASS (ccmode) == MODE_CC)
++ gcc_assert (XEXP (operands[1], 1) == const0_rtx);
++ else if (ccmode == QImode || ccmode == HImode)
++ FAIL;
++ else
++ {
++ ccreg = aarch64_gen_compare_reg (code, ccreg, XEXP (operands[1], 1));
++ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
++ }
+ }
+ )
+
## gcc/testsuite/gcc.target/aarch64/cmpbr-4.c (new) ##
@@
-: ------------ > 2: 9d1ac137bae6 aarch64: Merge mov<ALLI>cc with mov<GPF>cc
-: ------------ > 3: 0be75cc4c954 aarch64: Remove redundant checks
2: 357d94aec3a7 ! 4: 1ce592b5af98 aarch64: Merge mov<ALLI>cc with mov<GPF>cc
@@ Metadata
Author: Karl Meakin <karl.meakin@arm.com>
## Commit message ##
- aarch64: Merge mov<ALLI>cc with mov<GPF>cc
+ aarch64: Add `aarch64_comparison_operator_cc`
- The bodies of `mov<ALLI>cc` and `mov<GPF>cc` are identical, so merge
- them by using a new mode iterator that combines `ALLI` and `GPF`.
+ Deduplicate the checks against `ccmode` by extracting to a new
+ predicate.
gcc/ChangeLog:
- * config/aarch64/aarch64.md (mov<ALLI>cc): Merge with ...
- (mov<ALLI>cc): ... this.
- * config/aarch64/iterators.md(ALLI_GPF): New mode iterator.
+ * config/aarch64/aarch64.md(mov<ALLI_GPF:mode>cc): Use new predicate.
+ (mov<GPF:mode><GPI:mode>cc): Likewise.
+ (<neg_not_op><mode>cc): Likewise.
+ * config/aarch64/predicates.md (aarch64_comparison_operator_cc):
+ New predicate.
## gcc/config/aarch64/aarch64.md ##
@@
- )
- (define_expand "mov<mode>cc"
-- [(set (match_operand:ALLI 0 "register_operand")
-- (if_then_else:ALLI (match_operand 1 "aarch64_comparison_operator")
-- (match_operand:ALLI 2 "register_operand")
-- (match_operand:ALLI 3 "register_operand")))]
-+ [(set (match_operand:ALLI_GPF 0 "register_operand")
-+ (if_then_else:ALLI_GPF (match_operand 1 "aarch64_comparison_operator")
-+ (match_operand:ALLI_GPF 2 "register_operand")
-+ (match_operand:ALLI_GPF 3 "register_operand")))]
+ (define_expand "mov<ALLI_GPF:mode>cc"
+ [(set (match_operand:ALLI_GPF 0 "register_operand")
+- (if_then_else:ALLI_GPF (match_operand 1 "aarch64_comparison_operator")
++ (if_then_else:ALLI_GPF (match_operand 1 "aarch64_comparison_operator_cc")
+ (match_operand:ALLI_GPF 2 "register_operand")
+ (match_operand:ALLI_GPF 3 "register_operand")))]
""
- {
- enum rtx_code code = GET_CODE (operands[1]);
@@
- }
- )
+ rtx ccreg = XEXP (operands[1], 0);
+ enum machine_mode ccmode = GET_MODE (ccreg);
--(define_expand "mov<mode>cc"
-- [(set (match_operand:GPF 0 "register_operand")
-- (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator")
-- (match_operand:GPF 2 "register_operand")
-- (match_operand:GPF 3 "register_operand")))]
-- ""
-- {
-- enum rtx_code code = GET_CODE (operands[1]);
-- if (code == UNEQ || code == LTGT)
+- if (GET_MODE_CLASS (ccmode) == MODE_CC)
+- gcc_assert (XEXP (operands[1], 1) == const0_rtx);
+- else if (ccmode == QImode || ccmode == HImode)
- FAIL;
--
-- rtx ccreg = XEXP (operands[1], 0);
-- enum machine_mode ccmode = GET_MODE (ccreg);
+- else
++ if (GET_MODE_CLASS (ccmode) != MODE_CC)
+ {
+ ccreg = aarch64_gen_compare_reg (code, ccreg, XEXP (operands[1], 1));
+ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+@@
+
+ (define_expand "mov<GPF:mode><GPI:mode>cc"
+ [(set (match_operand:GPI 0 "register_operand")
+- (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator")
++ (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator_cc")
+ (match_operand:GPF 2 "register_operand")
+ (match_operand:GPF 3 "register_operand")))]
+ ""
+@@
+
+ rtx ccreg = XEXP (operands[1], 0);
+ enum machine_mode ccmode = GET_MODE (ccreg);
- if (GET_MODE_CLASS (ccmode) == MODE_CC)
- gcc_assert (XEXP (operands[1], 1) == const0_rtx);
- else if (ccmode == QImode || ccmode == HImode)
- FAIL;
- else
-- {
-- ccreg = aarch64_gen_compare_reg (code, ccreg, XEXP (operands[1], 1));
-- operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
-- }
-- }
--)
--
++ if (GET_MODE_CLASS (ccmode) != MODE_CC)
+ {
+ ccreg = aarch64_gen_compare_reg (code, ccreg, XEXP (operands[1], 1));
+ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+@@
+
(define_expand "<neg_not_op><mode>cc"
[(set (match_operand:GPI 0 "register_operand")
- (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator")
+- (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator")
++ (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator_cc")
+ (NEG_NOT:GPI (match_operand:GPI 2 "register_operand"))
+ (match_operand:GPI 3 "register_operand")))]
+ ""
+@@
+
+ rtx ccreg = XEXP (operands[1], 0);
+ enum machine_mode ccmode = GET_MODE (ccreg);
+- if (GET_MODE_CLASS (ccmode) == MODE_CC)
+- gcc_assert (XEXP (operands[1], 1) == const0_rtx);
+- else if (ccmode == QImode || ccmode == HImode)
+- FAIL;
+- else
++ if (GET_MODE_CLASS (ccmode) != MODE_CC)
+ {
+ ccreg = aarch64_gen_compare_reg (code, ccreg, XEXP (operands[1], 1));
+ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
- ## gcc/config/aarch64/iterators.md ##
+ ## gcc/config/aarch64/predicates.md ##
@@
- ;; Iterator for all 16-bit scalar floating point modes (HF, BF)
- (define_mode_iterator HFBF [HF BF])
+ return aarch64_get_condition_code (op) >= 0;
+ })
-+;; Iterator for all integer modes (up to 64-bit) plus all General Purpose
-+;; Floating-point registers (32- and 64-bit modes).
-+(define_mode_iterator ALLI_GPF [ALLI GPF])
++(define_predicate "aarch64_comparison_operator_cc"
++ (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
++ ordered,unlt,unle,unge,ungt")
++{
++ rtx ccreg = XEXP (op, 0);
++ enum machine_mode ccmode = GET_MODE (ccreg);
++
++ if (GET_MODE_CLASS (ccmode) == MODE_CC)
++ gcc_assert (XEXP (op, 1) == const0_rtx);
++ else if (ccmode == QImode || ccmode == HImode)
++ return false;
+
- ;; Iterator for all scalar floating point modes suitable for moving, including
- ;; special BF type and decimal floating point types (HF, SF, DF, TF, BF,
- ;; SD, DD and TD)
++ return true;
++})
++
+ (define_special_predicate "aarch64_equality_operator"
+ (match_code "eq,ne"))
+
-: ------------ > 5: 762baaa6470d aarch64: Remove unused pattern
--
2.50.1
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