[PATCH 2/4] RISC-V: strcmp [speed optimized]: use compressed registers wherever possible

[puranikvinit]

Replaces temporary registers (t0) with compressed registers (a4) in the
null detection loop, reducing instruction count and code size in
speed-optimized builds while maintaining identical logic.

Signed-off-by: puranikvinit <kvp933.vinit@gmail.com>
Reviewed-by: Christian Herber <christian.herber@oss.nxp.com>
---
 newlib/libc/machine/riscv/strcmp.S | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/newlib/libc/machine/riscv/strcmp.S b/newlib/libc/machine/riscv/strcmp.S
index 25ad9ef2e..405f2f655 100644
--- a/newlib/libc/machine/riscv/strcmp.S
+++ b/newlib/libc/machine/riscv/strcmp.S
@@ -48,12 +48,12 @@ strcmp:
     REG_L a2, \i*SZREG(a0)
     REG_L a3, \i*SZREG(a1)
 
-    and   t0, a2, a5
+    and   a4, a2, a5
     or    t1, a2, a5
-    add   t0, t0, a5
-    or    t0, t0, t1
+    add   a4, a4, a5
+    or    a4, a4, t1
 
-    bne   t0, t2, .Lnull\i
+    bne   a4, t2, .Lnull\i
     .if \i+1-\n
       bne   a2, a3, .Lmismatch
     .else
-- 
2.34.1