[PATCH 09/12] RISC-V: memset() size optimized version: Use compressed registers

[Kito Cheng]

LGTM

On Wed, Apr 9, 2025 at 2:49 PM m fally <marlene.fally@gmail.com> wrote:
>
> From: Eric Salem <ericsalem@gmail.com>
>
> Swap register t1 with a3, so that the affected instructions can be compressed.
>
> Reviewed-by: Christian Herber <christian.herber@oss.nxp.com>
> Reviewed-by: m fally <marlene.fally@gmail.com>
> Signed-off-by: Eric Salem <ericsalem@gmail.com>
> ---
>  newlib/libc/machine/riscv/memset.S | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/newlib/libc/machine/riscv/memset.S b/newlib/libc/machine/riscv/memset.S
> index a717ae7fb..fac0f73a2 100644
> --- a/newlib/libc/machine/riscv/memset.S
> +++ b/newlib/libc/machine/riscv/memset.S
> @@ -14,13 +14,13 @@
>  .type  memset, @function
>  memset:
>  #if defined(PREFER_SIZE_OVER_SPEED) || defined(__OPTIMIZE_SIZE__)
> -  mv t1, a0
> +  mv a3, a0
>    beqz a2, 2f
>
>  1:
> -  sb a1, 0(t1)
> +  sb a1, 0(a3)
>    add   a2, a2, -1
> -  add   t1, t1, 1
> +  add   a3, a3, 1
>    bnez a2, 1b
>
>  2:
> --
> 2.49.0
>