[PATCH][Newlib] arm: Fix the SP used in setting stack limit for standalone application.

[Srinath Parvathaneni]

Hi,

When the processor by default starts in USER mode, in __stack_init
function of crt0.s the stack limit register is not getting set
correctly for standalone application. This is because the register r3
used to set this stack limit register is not updated with correct stack
pointer value. This patch fixes this issue and updates r3 with correct
stack pointer value.

Regression tested on arm-none-eabi target for newlib and newlib-nano and found
no regressions.

Ok for newlib master?

Regards,
Srinath.

libgloss/ChangeLog:

2023-03-03  Srinath Parvathaneni<srinath.parvathaneni@arm.com>

	* arm/crt0.S (__stack_init): Update r3 value before mode checking.

newlib/ChangeLog:

2023-03-03  Srinath Parvathaneni<srinath.parvathaneni@arm.com>

	* libc/sys/arm/crt0.S (__stack_init): Update r3 value before mode
         checking.
-------------- next part --------------
diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S
index 78515180bf06f1da37669e4c7e6608c76e1b096d..79ae1e2511783d6b834bd1ac278316ae04ea2ec8 100644
--- a/libgloss/arm/crt0.S
+++ b/libgloss/arm/crt0.S
@@ -149,13 +149,12 @@
 #if (__ARM_ARCH_PROFILE != 'M')
 	/* Following code is compatible for both ARM and Thumb ISA.  */
 	mrs	r4, CPSR
+	mov	r3, sp /* Save input SP value.  */
 	/* Test mode bits - in User of all are 0.  */
 	tst	r4, #(CPSR_M_MASK)
 	/* "eq" means r4 AND #0x0F is 0.  */
 	beq	.Lskip_cpu_modes
 
-	mov	r3, sp /* Save input SP value.  */
-
 	/* FIQ mode, interrupts disabled.  */
 	mov	r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK)
 	msr	CPSR_c, r1
diff --git a/newlib/libc/sys/arm/crt0.S b/newlib/libc/sys/arm/crt0.S
index 6b01d8a88b77f44b1ba495aa1f69156f12749527..121246cfaf1ea197c271e434fe0c05a3aba8fb6a 100644
--- a/newlib/libc/sys/arm/crt0.S
+++ b/newlib/libc/sys/arm/crt0.S
@@ -149,13 +149,12 @@
 #if (__ARM_ARCH_PROFILE != 'M')
 	/* Following code is compatible for both ARM and Thumb ISA.  */
 	mrs	r4, CPSR
+	mov	r3, sp /* Save input SP value.  */
 	/* Test mode bits - in User of all are 0.  */
 	tst	r4, #(CPSR_M_MASK)
 	/* "eq" means r4 AND #0x0F is 0.  */
 	beq	.Lskip_cpu_modes
 
-	mov	r3, sp /* Save input SP value.  */
-
 	/* FIQ mode, interrupts disabled.  */
 	mov	r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK)
 	msr	CPSR_c, r1