[PATCH v2][Newlib] arm: Restrict processor mode change when in hypervisor mode.

Richard Earnshaw Richard.Earnshaw@foss.arm.com
Thu Mar 2 13:05:22 GMT 2023

On 23/02/2023 17:10, Srinath Parvathaneni wrote:
> Hi All,
> In _stack_init function of crt0.S file, when the current mode is not 
> user mode,
> all the processor modes are parsed and the corresponding stack limit are 
> set for
> these modes for all A-profile and R-profile CPU's. But when the current 
> processor
> mode is hypervisor mode, changing to any other mode using CPSR will 
> result in an
> illegal instruction as per Arm-arm and simulator throws undefined 
> instruction
> exception.

The reference to a simulator here is confusing.  You might have found 
this on one, but it's a reflection of the way the architecture is 
specified and not specific to running under simulation.

> This patch prevent the change of hypervisor mode to any other mode in 
> _stack_init
> function in crt0.S files.
> Regression tested on arm-none-eabi target for newlib and newlib-nano and 
> found
> no regressions.
> Ok for newlib master?
> Regards,
> Srinath.
> libgloss/ChangeLog:
> 2023-02-23  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
>          * arm/crt0.S (_stack_init): Add check for hypervisor mode.
> newlib/ChangeLog:
> 2023-02-23  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
>          * libc/sys/arm/crt0.S (_stack_init): Add check for hypervisor 
> mode.

-	/* Test mode bits - in User of all are 0.  */
-	tst	r4, #(CPSR_M_MASK)
-	/* "eq" means r4 AND #0x0F is 0.  */
+	mov	r3, sp
+	ands	r1, r4, #(CPSR_M_MASK)
+	beq	.Lskip_cpu_modes
+	cmp	r1, #(CPSR_M_HYP)

You don't mention anywhere why you've moved the instruction that copies 
SP into R3 before the user-mode check.  I think it's probably right, but 
I think really that's a separate issue that deserves a separate patch 
(even though it's pretty trivial).

So please can you resend as two patches, the first fixing the SP->r3 
copy and the second for the hypervisor mode issue.


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