Help porting newlib to a new CPU architecture (sorta)
Wed Jul 7 00:29:00 GMT 2021
*@Paul*, I am looking at the code you maintain. I downloaded Eclipse for C
/ C ++ and I am currently cloning gcc repository.
My intention is to read carefully your code and rewrite the less possible.
Also I have looked up that internals gcc manual mentioned above, and it is
really all I need to read now. I am very thankful to you,
It is really recomfortating to find out the very right person to ask for
help. Really appreciate it.
I have not had time yet to check yet avr, h8, m6809 codes, but seems also
candidate alternatives, so,
I will note below the characteristics of my architecture, in depth, to help
us decide which one is closer to mine.
*4x8b GP Registers*- A, Accumulator, Argc
- B, Summand, Auxiliar in indirections for higher 8 bit addressing
- C, Auxiliar, Auxiliar used in indirections for mid 8 bit addressing,
String register (not connected to ALU but it is connected to other REGS via
- D, Auxiliar, Auxiliar used in indirections for lower 8 bit addressing.
*Memory Address Registers*Those point to RAM for in/redirections and look
ups into RAM.
- M0 lower 8 bit
- M1 mid 8 bit
- M2 high 8 bit
* M2 + M1 + M0 conforms a full 24 bit address.
*Stack registers:*- SR0 stores M0 on push while calling a new branch. Pops
to M0 on return. Allows REG B to be pushed.-
- SR1 stores M1 on push while calling a new branch. Pops to M1 on return.
Allows REG C to be pushed.
- SR2 stores M1 on push while calling a new branch. Pops to M2 on return.
Allows REG D to be pushed.
*Output register*- Stores temporarily one char to be output. It will be
replaced by a text based GPU with 64K of memory to allow cursor
operations on the lcd and also speed up printing, with a separate
- Carry flag
- Zero flag
- Parity flag (not yet shown not used)
- Borrow flag ('' '' '' '' '')
*So It's basically an automat, with stack, with 8 bit ALU, with 4 GP
registers, with 24bit addressable memory, and 24bit max length push/pop
1) Let's decide the appropiate basis first.
2) As a side part, I am able now I read the code, to better understand how
gcc relates to gas, and, now I am able to understand also how would it be
to just, "make gcc to spit my pseudoassy" and just use my assembler.
Knowing this is possible, I will apart the idea for the moment as plab - B
to the purpose of compiling existing C / C ++ 8 bit software into Libre 8,
with at least GCC. (This is good at least, and very very much easier :)) ).
Now I am interested into use the full chain, including gas, with the
"internals" manual provided. If everything fails or I got overwhelmed, I
got plan B.
Thank you all,
El mié, 7 jul 2021 a las 1:50, Paul Koning (<firstname.lastname@example.org>)
> > On Jul 6, 2021, at 6:00 PM, Joel Sherrill <email@example.com> wrote:
> > I think you might get some ideas from the old m6809 port of gcc
> > http://vectrexc.malban.de/documentation/gcc-6809-documentation
> > That was an 8 bit CPU with only 64k memory space if I remember everything
> > correctly.
> pdp11 also has 64k of address space, and the current gcc still supports it.
> > I think given an add with carry, gcc can be taught to use 8 bit
> > in sequence on larger types. I recall seeing this on the h8 or avr.
> pdp11 also, for 32 or 64 bit integers given 16 bit arithmetic. You don't
> actually need add with carry, but having one makes the code more compact.
> I think gcc core will do that flavor if the target code doesn't teach it
> the more efficient way (which is easy to do).
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