[PATCH][AArch64][SVE][Newlib] Initialize SVE system registers.

[Richard Earnshaw (lists)]

On 26/10/2018 10:27, Tamar Christina wrote:
> Hi All,
> 
> This patch initializes the SVE system registers if available
> and initializes the vector length to the maximum supported.
> 
> This is done according to the SVE specification [1].
> 
> [1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
> 
> Compiled aarch64-none-elf and no issues.
> 
> Ok for master?
> 
> PS. I don't have commit rights so if OK can someone commit for me?
> 

Pushed.

R.

> Thanks,
> Tamar
> 
> 
> 0001-AArch64-SVE-Initialize-SVE-system-registers.patch
> 
> From 4cb00e8cc316d309cb3a380feb1f07f8406c7a0d Mon Sep 17 00:00:00 2001
> From: Tamar Christina <tamar.christina@arm.com>
> Date: Fri, 26 Oct 2018 10:18:17 +0100
> Subject: [PATCH] [AArch64][SVE] Initialize SVE system registers.
> 
> This patch initializes the SVE system registers if available
> and initializes the vector length to the maximum supported.
> 
> This is done according to the SVE specification [1].
> 
> [1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
> ---
>  libgloss/aarch64/cpu-init/rdimon-aem-el3.S | 27 ++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/libgloss/aarch64/cpu-init/rdimon-aem-el3.S b/libgloss/aarch64/cpu-init/rdimon-aem-el3.S
> index 9edbccde5d..e00f0b2c8e 100644
> --- a/libgloss/aarch64/cpu-init/rdimon-aem-el3.S
> +++ b/libgloss/aarch64/cpu-init/rdimon-aem-el3.S
> @@ -145,6 +145,33 @@ _flat_map:
>  	dsb	sy
>  	msr	sctlr_el3, x0
>  	isb
> +
> +	/* Determine if SVE is available.  */
> +       mrs      x0, id_aa64pfr0_el1
> +       tbz      x0, 32, .Lnosve
> +
> +       /* set up CPTR_EL3.TZ to 1.  */
> +       mrs     x0, cptr_el3
> +
> +       /* TZ is bit 8 of CPTR_EL3.  */
> +       orr     x0, x0, #0x100
> +       msr     cptr_el3, x0
> +       isb
> +
> +       /* set up vector lenght in ZCR_EL3 (4 LSB).  */
> +       mov     x2, #0xF
> +
> +       /* Try to set the maximum value supported by the architecture (2048).
> +	  SVE Arch.
> +
> +	    "If this field is set to a value that is not supported by the
> +	    implementation then reading the register must return the highest
> +	    supported vector length that is less than the value written."  */
> +       mrs     x1, s3_6_c1_c2_0                /* mrs  x1, zcr_el3.  */
> +       bfi     x1, x2, 0, 4
> +       msr     s3_6_c1_c2_0, x1                /* msr  zcr_el3, x1.  */
> +       isb
> +.Lnosve:
>  	ret
>  
>  	.data
>