[ARM] Initializing TTBR0 to inner/outer WB

[Jiong Wang]

While running tests on internal systems, we identified an issue in the
startup code for newlib on AArch32 systems with Multiprocessor
Extensions to the architecture.

The issue is we were configuring page table flags to be Inner
cacheable/Outer non-cacheable, while for at least architectures with
Multiprocessor Extension, we'd configure it to Inner/Outer write-back, no
write-allocate, and cacheable.

The attached patch fixes this, and no regression on arm-none-eabi
bare-metal tests.

OK for trunk?

Thanks.

2016-03-21  Jiong Wang  <jiong.wang@arm.com>

libgloss/
   * arm/cpu-init/rdimon-aem.S: Set TTBR0 to inner/outer
   cacheable WB, and no allocate on WB for arch with multiprocessor
   extension.

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