__getreent in libgloss

Stefan Wallentowitz stefan.wallentowitz@tum.de
Thu Nov 6 08:56:00 GMT 2014

On 05.11.2014 18:06, Joel Sherrill wrote:
> But is the same information available for current core number and
> maximum cores available in a uniprocessor or1k CPU?
Only after the latest architecture manual revision. Thats why there will 
be multilib or similar for multicore support in the toolchain to still 
support old implementations. All current work supports it.
> Does the or1k simulator do multicore? Does it have synchronization
> instructions? Just curious since SMP RTEMS on or1k is something
> I really hadn't thought about. We already support ARM, SPARC,
> PowerPC, and x86.
or1ksim does not allow multiple cores, which is a major problem. It 
nevertheless has the multicore support in it (SPR_COREID reads 0, 
SPR_NUMCORES 1) plus the LL/SC instructions (lwa and swa). qemu does not 
have multicore, but I am not sure, but executes the code also correctly 
in uniprocessor mode.
The current HDL implementation mor1kx supports it fully. Using fusesoc 
you can easily build a Verilator simulation from it (which is of course 
slower than an ISS). Contact me, if you need a QuickStart.
We use Multicore or1k in our projects and would be happy to try RTEMS. 
What do you think is the required effort? Linux SMP for OpenRISC already 


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