First time configuring/linking with newlib...

Likely, Grant
Tue Mar 11 16:43:00 GMT 2003

Don't forget that even though your .data section is located in RAM, it is
initialized from values in ROM.  You linker script needs to put .data into
both ROM and RAM; The "Virtual Memory Address" (VMA) is the location in RAM
where program looks for .data, and the "Load Memory Address" (LMA) is where
.data is actually put by the loader (into ROM).  Then your boot code in
crt0.S must copy .data from ROM to RAM before jumping into main().

Modify your linker script like this:

change:  .data : AT(ADDR(.text)+SIZEOF(.text)) { *(.data) } > ram
to:      .data : { *(.data) } >ram AT>rom

(I don't think you need the AT(...) when you are redirecting using > or AT>)

You will also need to add some symbols so that you know where .data starts
and ends in both ROM and RAM.


-----Original Message-----
From: Dan Fowell []
Sent: Tuesday, March 11, 2003 8:27 AM
Subject: RE: First time configuring/linking with newlib...

Hey Jeff, thanks so much for your help!  Per your suggestions I've now got
all the needed stubs in for the low-level system calls (write, close,
fstat,etc...) and after adding .fixup and .got2 sections in my linker file
the .bss error went away, and sprintf now actually works great from RAM.

Unfortunately it's too early to celebrate because I can't get it working
from my ROM.  I wonder if it has something to do with the relocation aspects
of .got2 and .fixup?  Maybe something is wrong with my ROM linker file?  The
code doesn't crash, but the sprintf just doesn't do anything although
everything compiles/links OK.  When I display the string after the sprintf
statement it's completely empty.  .got2 and .fixup should be located to RAM
space, right?  Is there anything special I need to do when using newlib in
ROM instead of RAM?

Thanks again,

Below is the pertinent section of the working RAM linker file and the not
yet working ROM linker file:

RAM Version:
.text : { *(.text) *(.rodata) *(.init) *(.fini) } > mem
.data ALIGN (4) : { *(.data) *(.sdata) *(.sdata2) } > mem
.bss ALIGN (4) : { *(.bss) *(.sbss) } > mem
.got2 ALIGN (4) : { *(.got2)} > mem
.fixup ALIGN (4) : { *(.fixup)} > mem

PROVIDE (__stack = .);
_end = .;

ROM Version:
.text : { *(.text) *(.rodata) *(.rdata) *(.init) *(.fini) *(.sec1) }  > rom
.data : AT(ADDR(.text)+SIZEOF(.text)) { *(.data) } > ram
.got2 : AT(ADDR(.text)+SIZEOF(.text)+SIZEOF(.data)) { *(.got2) } > ram
.fixup : AT(ADDR(.text)+SIZEOF(.text)+SIZEOF(.data)+SIZEOF(.got2)) {
*(.fixup) } > ram
.sdata :
AT(ADDR(.text)+SIZEOF(.text)+SIZEOF(.data)+SIZEOF(.got2)+SIZEOF(.fixup)) {
*(.sdata) *(.sdata2) } > ram
.bss ALIGN (4) : { *(.bss) *(.sbss)} > ram

_end =.;

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