[newlib-cygwin] riscv: avoid misaligned accesses if __riscv_misaligned_slow

[Kito Cheng]

https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;h=d110c88b4e74abd376bbd13a0930a8f78171366a

commit d110c88b4e74abd376bbd13a0930a8f78171366a
Author: Gedare Bloom <gedare@rtems.org>
Date:   Thu Apr 30 11:10:53 2026 -0600

    riscv: avoid misaligned accesses if __riscv_misaligned_slow
    
    The configure rule for misaligned accesses is too wide by including
    __riscv_misaligned_fast or __riscv_misaligned_slow for enabling the
    HW supported misaligned access.

Diff:
---
 newlib/configure    | 2 +-
 newlib/configure.ac | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/newlib/configure b/newlib/configure
index 92df986ef..dd4153173 100755
--- a/newlib/configure
+++ b/newlib/configure
@@ -6723,7 +6723,7 @@ if ${newlib_cv_hw_misaligned_access+:} false; then :
   $as_echo_n "(cached) " >&6
 else
     cat > conftest.c <<EOF
-#if __riscv_misaligned_fast || __riscv_misaligned_slow
+#if __riscv_misaligned_fast
 void misalign_access_supported(void) {}
 #else
 #error "misaligned access is not supported"
diff --git a/newlib/configure.ac b/newlib/configure.ac
index a4807830e..4640e69c5 100644
--- a/newlib/configure.ac
+++ b/newlib/configure.ac
@@ -555,7 +555,7 @@ if test "x${newlib_hw_misaligned_access}" = "x"; then
   AC_CACHE_CHECK([if $CC has enabled misaligned hardware access],
               [newlib_cv_hw_misaligned_access], [dnl
   cat > conftest.c <<EOF
-#if __riscv_misaligned_fast || __riscv_misaligned_slow
+#if __riscv_misaligned_fast
 void misalign_access_supported(void) {}
 #else
 #error "misaligned access is not supported"