[PATCH 002/120] MIPS: R5900: Trap the RDHWR instruction as an SQ address exception

[Fredrik Noring]

On Sat, Dec 12, 2020 at 11:36:35AM +0000, Maciej W. Rozycki wrote:
>  Unlike TLS pointer access, specifically using $3 as rt, which has been 
> made a part of the Linux ABI, they're not supposed to be referred with 
> pre-R2 code.  After all RDHWR was only introduced with R2.
> 
>  Indeed there's emulation code in the kernel for those encodings even with 
> pre-R2 hardware, but it is not guaranteed to give sensible results, and 
> given the circumstances I'm not sure what it really is for, e.g. what is 
> SYNCI_Step for with processors that do not implement SYNCI?  The cycle 
> counter register may be absent too, so even emulated accesses will return 
> rubbish; gettimeofday(2) is the standard interface.
> 
>  So I think we can safely ignore them, just as we can any ULR access with 
> rt != $3.  Unlike standardised TLS pointer accesses such instructions 
> won't appear in compiler-generated code and whoever uses them in handcoded 
> assembly or otherwise generated machine code will have to make sure they 
> make sense for their application (yes, there's rubbish code out there, 
> e.g. Firefox has a JIT that unconditionally produces MIPS R2 code even if 
> the piece of software has been compiled for an older ISA revision, and 
> having not verified that the CPU it runs on actually supports the R2 ISA, 
> but that's just the usual imperfection of the world; you just can't fix it 
> all).

Many thanks, that resolves it! I'll write it up in the commit message.

Fredrik