[PATCH] PPC fenv fixes.

[Steven Munroe]

Steven Munroe wrote:
> Jakub Jelinek wrote:
>   
>> On Tue, Mar 27, 2007 at 11:09:28AM -0500, Steven Munroe wrote:
>>     
>>> 2007-03-26  Steven Munroe  <sjmunroe@us.ibm.com>
>>>
>>> 	* sysdeps/powerpc/fpu/feupdateenv.c: Change mask to merge exceptions
>>> 	from env.
>>>       
>> Will that actually raise SIGFPE signals when exceptions are enabled?
>> From my reading of POSIX that's what should happen with the
>> `old' exceptions (and other arches are calling feraiseexcept that will do
>> that).  I didn't add a testcase for it because I'm not 100% sure about that.
>>   
>>     
> hmmm not unless the SIGFPE is eanbled by the MSR FE bits. So we will
> need to call __fe_nomask_env() in feupdateenv similar to what we do in
> feenableexcept(). Probably should add the __fe_mask_env() call for when
> the application remasks FP exceptions. This allows the hardware to run
> faster when we are taking the default action.
>
> I will rework the patch.
>   
Merges my patch with one from Peter Bergner to use the prctl system to
eanble/disable FP exception when ever the FPSCR exeptions bits:
  FPSCR_VE,        /* invalid operation exception enable */
  FPSCR_OE,        /* overflow exception enable */
  FPSCR_UE,        /* underflow exception enable */
  FPSCR_ZE,        /* zero divide exception enable */
  FPSCR_XE,        /* inexact exception enable */

Change from all disabled to any enabled or any eanbled to all disabled.
This check was already in feenableexcept(). This patch adds the
appropriate eanble/disable calls to fedisableexcept() and __feupdateenv().


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