adding _SC_LEVEL_*CACHE* support

[David Mosberger]

Today it was brought to my attention that the following sysconf
constants

   _SC_LEVEL1_ICACHE_SIZE
   _SC_LEVEL1_ICACHE_ASSOC
   _SC_LEVEL1_ICACHE_LINESIZE
   _SC_LEVEL1_DCACHE_SIZE
   _SC_LEVEL1_DCACHE_ASSOC
   _SC_LEVEL1_DCACHE_LINESIZE
   _SC_LEVEL2_CACHE_SIZE
   _SC_LEVEL2_CACHE_ASSOC
   _SC_LEVEL2_CACHE_LINESIZE
   _SC_LEVEL3_CACHE_SIZE
   _SC_LEVEL3_CACHE_ASSOC
   _SC_LEVEL3_CACHE_LINESIZE
   _SC_LEVEL4_CACHE_SIZE
   _SC_LEVEL4_CACHE_ASSOC
   _SC_LEVEL4_CACHE_LINESIZE

do not return useful values on ia64.  That's reasonably easy to fix by
peeking into /proc/pal/cpu0/cache_info and arbitrarily assuming that
all CPUs have the same cache structure.  What's no so easy to fix is
that these constants assume that only the L1 cache may be split.  Is
it possible to introduce additional constants of this sort to support
CPUs which have split caches at higher levels?  Perhaps it would make
sense to add _ICACHE_ variants L2-L4 with the understanding that the
normal _CACHE_ variants would refer to the D-cache in case that level
is split?

	--david