[PATCH] riscv: Optimize vectorized memory routines with ifunc dispatch

[Zheng Ziyang]

Hi Jeff, Hi Peter,

Thanks for the detailed feedback.

I apologize for the bulk replacement approach in this v2. The current submission is tuned for a particular platform. Since details of that platform cannot be disclosed at this time, we used K3 benchmark data to illustrate the performance characteristics. We understand your concern that the current changes appear to be optimized for a specific micro-architecture.

At the appropriate time, we will provide detailed benchmark data from the glibc performance suite to justify where micro-architecture specific variants are needed. We agree that the correct way forward is to keep the standard vector implementations as-is, and add uarch-specific variants when they show meaningful improvements. Future submissions will include both a more efficient generic implementation that works across different VLENB configurations, and separate uarch-specific branches tuned for particular cores.

This submission was also intended to gauge the community’s preference and attitude toward RV implementations. Going forward, we will focus on targeted improvements to the existing code, and provide clear justification when introducing uarch-specific variants.

Best regards,
Ziyang
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