[PATCH v5 11/18] riscv: Add RVV strcmp for multiarch and non-multiarch

[Peter Bergner]

On 2/3/26 9:05 AM, Yao Zihong wrote:
> Co-authored-by: Hau Hsu <hau.hsu@sifive.com>
> Co-authored-by: Jerry Shih <jerry.shih@sifive.com>
> Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
> ---
>  sysdeps/riscv/multiarch/strcmp-generic.c      | 24 +++++
>  sysdeps/riscv/multiarch/strcmp-vector.S       | 24 +++++
>  sysdeps/riscv/rvv/strcmp.S                    | 93 +++++++++++++++++++
>  .../unix/sysv/linux/riscv/multiarch/Makefile  |  3 +
>  .../linux/riscv/multiarch/ifunc-impl-list.c   |  5 +
>  .../unix/sysv/linux/riscv/multiarch/strcmp.c  | 56 +++++++++++
>  6 files changed, 205 insertions(+)
>  create mode 100644 sysdeps/riscv/multiarch/strcmp-generic.c
>  create mode 100644 sysdeps/riscv/multiarch/strcmp-vector.S
>  create mode 100644 sysdeps/riscv/rvv/strcmp.S
>  create mode 100644 sysdeps/unix/sysv/linux/riscv/multiarch/strcmp.c


This LGTM.  I'm currently testing this and will push it if the
testsuite run is clean.

Reviewed-by: Peter Bergner <bergner@tenstorrent.com>

Peter