[PATCH] LoongArch: feclearexcept: skip clearing CAUSE

[caiyinyu]

LGTM.



在 2026/3/19 下午4:33, Xi Ruoyao 写道:
> The comment explaining the reason to clear CAUSE does not make any
> sense: it says the next "CTC" instruction would raise the FP exception
> of which both the CAUSE and ENABLE bits are set, but LoongArch does not
> have the CTC instruction.  LoongArch has the movgr2fcsr instruction but
> movgr2fcsr never raises any FP exception, different from the MIPS CTC
> instruction.
>
> So we don't really need to care CAUSE at all.
>
> Signed-off-by: Xi Ruoyao <xry111@xry111.site>
> ---
>   sysdeps/loongarch/fpu/fclrexcpt.c | 7 ++-----
>   1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/sysdeps/loongarch/fpu/fclrexcpt.c b/sysdeps/loongarch/fpu/fclrexcpt.c
> index 7ce166659b..0c95069a1d 100644
> --- a/sysdeps/loongarch/fpu/fclrexcpt.c
> +++ b/sysdeps/loongarch/fpu/fclrexcpt.c
> @@ -31,11 +31,8 @@ __feclearexcept (int excepts)
>     /* Read the complete control word.  */
>     _FPU_GETCW (cw);
>   
> -  /* Clear exception flag bits and cause bits.  If the cause bit is not
> -     cleared, the next CTC instruction (just below) will re-generate the
> -     exception.  */
> -
> -  cw &= ~(excepts | (excepts << CAUSE_SHIFT));
> +  /* Clear exception flag bits.  */
> +  cw &= ~excepts;
>   
>     /* Put the new data in effect.  */
>     _FPU_SETCW (cw);