[PATCH v2] riscv: Fix RV32 libthread_db THREAD_SELF register layout

[Peter Bergner]

On 6/24/26 6:29 AM, Shengwen Cheng wrote:
> The RISC-V libthread_db THREAD_SELF descriptor currently assumes 64-bit
> general-register slots:
> 
>   REGISTER (64, 64, 4 * 8, ...)
> 
> That is correct for RV64, where tp/x4 is at byte offset 4 * 8 in the
> general register set.  On RV32, general-register slots are 32-bit wide,
> so tp/x4 is at byte offset 4 * 4.
> 
> Using the RV64 layout on RV32 makes libthread_db read the wrong thread
> pointer value and prevents GDB from enabling pthread-aware thread
> debugging.
> 
> Use a helper macro to pass the RISC-V register size into the
> DB_THREAD_SELF definition.
> ---
>  sysdeps/riscv/nptl/tls.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/sysdeps/riscv/nptl/tls.h b/sysdeps/riscv/nptl/tls.h
> index b2e0f3c249..1e46e93669 100644
> --- a/sysdeps/riscv/nptl/tls.h
> +++ b/sysdeps/riscv/nptl/tls.h
> @@ -96,8 +96,9 @@ typedef struct
>  
>  /* Informs libthread_db that the thread pointer is register 4, which is used
>   * to know how to do THREAD_SELF.  */
> -# define DB_THREAD_SELF \
> -  REGISTER (64, 64, 4 * 8, - TLS_TCB_OFFSET - TLS_PRE_TCB_SIZE)
> +# define DB_THREAD_SELF_REGISTER(bits) \
> +  REGISTER (bits, bits, 4 * bits / 8, - TLS_TCB_OFFSET - TLS_PRE_TCB_SIZE)
> +# define DB_THREAD_SELF DB_THREAD_SELF_REGISTER (__riscv_xlen)
>  
>  /* Access to data in the thread descriptor is easy.  */
>  # include <tcb-access.h>

LGTM.

Reviewed-by: Peter Bergner <bergner@tenstorrent.com>

Are you able to push this yourself or do you need help with that?
If you need help, then do you have a GNU copyright assignment on file
or are you submitting this under DCO?  If the latter, you'll need to
add a Signed-off-by: ... to your submission.  Just let me know what
you want that to look like if you need me to push the commit.

Peter