[PATCH v2] RISC-V: add multiarch RVV support for memcpy using FMV IFUNC

[Jeffrey Law]

On 1/17/2025 6:01 AM, daichengrong wrote:
>
>
> On 2025/1/17 07:46, Andrew Waterman wrote:
>> On Thu, Jan 16, 2025 at 1:31 AM 戴成荣<daichengrong@iscas.ac.cn> wrote:
>>> With RISC-V GCC Function multi-versioning IFUNC support,glibc could utilize some new RISC-V CPUs with new extensions such as Vector to re-realize or speed up some functions like memcpy.
>>>
>>> +ENTRY (__memcpy_vector)
>>> +    beq     a2, zero, L(ret)
>> This branch should be deleted; the strip-mine loop below does the
>> correct thing for a2=0.  Including the branch is an anti-optimization:
>> it speeds up the uncommon case of size-0 memcpy at the expense of the
>> common case.
> Thanks! This branch has been deleted.
Note Peter installed Yow Zihong's version which is functionally 
equivalent.  So this patch is obsolete.

Jeff
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