[PATCH v1 2/3] riscv: Add RVV implementation __strcpy_vector

[Yao Zihong]

> Your understanding is correct, but FWIW, I've yet to hear of an
> implementation actually doing this.

Both of the platforms tested (SpacemiT M1 and K230 with C908 cores)
exhibit this behavior.

>
> FWIW, reading vl should not be a slow operation on most
> implementations, even in the presence of fault-only-first loads.
> Performant implementations will speculate that fault-only-first loads
> don't fault, so that the CSR read doesn't need to wait for the
> fault-only-first load to execute.  (Of course, such implementations
> need to flush the pipeline following a misspeculation, but that will
> happen whether or not software reads vl--it is a sunk cost.)  Going
> out of one's way to avoid reading vl is probably an over-optimization
> for a particular microarchitecture's quirks.

That makes sense – if avoiding vl reads is really only relevant for a few
specific implementations, then it might be seen as an over-optimization.
In that case, would it make sense to agree on a small set of representative
RVV platforms (e.g. covering low-end, mid-range, and high-end) to guide such
decisions? That might help provide common reference points and make future
RVV optimization discussions smoother. For example, would something like
SG2044 be considered representative on the high-end side?

Zihong