[PATCH v1 3/3] riscv: Enable RVV strcpy in both ifunc-impl-list and resolver

[Yao Zihong]

This patch wires up the RVV implementation and enables runtime selection
on both sides.

- Add __strcpy_vector to ifunc-impl-list.c, guarded by hwprobe result
  of the V extension.
- Extend select_strcpy_ifunc in strcpy.c to also check dl_hwcap and
  return __strcpy_vector when COMPAT_HWCAP_ISA_V is present.
- Keep __strcpy_generic as the fallback for systems without V.

Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
---
 sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c | 8 ++++++++
 sysdeps/unix/sysv/linux/riscv/multiarch/strcpy.c          | 3 +++
 2 files changed, 11 insertions(+)

diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c b/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c
index 8e14560b65..c82e4738c4 100644
--- a/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c
+++ b/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c
@@ -27,12 +27,18 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
   size_t i = max;
 
   bool fast_unaligned = false;
+  bool rvv_ext = false;
 
   struct riscv_hwprobe pair = { .key = RISCV_HWPROBE_KEY_CPUPERF_0 };
   if (__riscv_hwprobe (&pair, 1, 0, NULL, 0) == 0
       && (pair.value & RISCV_HWPROBE_MISALIGNED_MASK)
           == RISCV_HWPROBE_MISALIGNED_FAST)
     fast_unaligned = true;
+  
+  struct riscv_hwprobe ext_pair = { .key = RISCV_HWPROBE_KEY_IMA_EXT_0 };
+  if (__riscv_hwprobe (&ext_pair, 1, 0, NULL, 0) == 0
+     && (ext_pair.value & RISCV_HWPROBE_IMA_V))
+   rvv_ext = true;
 
   IFUNC_IMPL (i, name, memcpy,
 	      IFUNC_IMPL_ADD (array, i, memcpy, fast_unaligned,
@@ -40,6 +46,8 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
 	      IFUNC_IMPL_ADD (array, i, memcpy, 1, __memcpy_generic))
   
   IFUNC_IMPL (i, name, strcpy,
+	      IFUNC_IMPL_ADD (array, i, strcpy, rvv_ext,
+           		      __strcpy_vector)
 	      IFUNC_IMPL_ADD (array, i, strcpy, 1, __strcpy_generic))
   return 0;
 }
diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/strcpy.c b/sysdeps/unix/sysv/linux/riscv/multiarch/strcpy.c
index 473fa7768d..04164885c3 100644
--- a/sysdeps/unix/sysv/linux/riscv/multiarch/strcpy.c
+++ b/sysdeps/unix/sysv/linux/riscv/multiarch/strcpy.c
@@ -32,10 +32,13 @@
 extern __typeof (__redirect_strcpy) __libc_strcpy;
 
 extern __typeof (__redirect_strcpy) __strcpy_generic attribute_hidden;
+extern __typeof (__redirect_strcpy) __strcpy_vector attribute_hidden;
 
 static inline __typeof (__redirect_strcpy) *
 select_strcpy_ifunc (uint64_t dl_hwcap, __riscv_hwprobe_t hwprobe_func)
 {
+  if (dl_hwcap & COMPAT_HWCAP_ISA_V)
+    return __strcpy_vector;
   return __strcpy_generic;
 }
 
-- 
2.47.2