[PATCH v3 0/3] riscv: tidy memcpy_noalignment for Zc-friendly encoding

[Yao Zihong]

Changes since v2:
------------------
- Removed the needless renames in patch 1.
- Dropped the inaccurate “favors compressed encodings” wording for the 
  single-andi fold in patch 2.
- Fixed comment wording in patch 1.

Patches 1 and 2 incorporate Peter’s feedback from v2. Additional comment clarifications
were also made in patch 1, so I have not carried forward his Reviewed-by tag.

Changes since v1:
------------------
- Fixed indentation issues in patches 1–3
- Dropped patch 4 (no longer necessary)

This series applies small, localized clean-ups in
sysdeps/riscv/multiarch/memcpy_noalignment.S to be friendlier to Zc*
compressed encodings and to slightly ease front-end pressure.  There is
no functional change: ABI/clobbers, control flow and memory semantics
remain the same.

Summary of changes
------------------
* 1/3  Use Zca-friendly temporaries
* 2/3  Fold SZREG/BLOCK_SIZE alignment sequences to a single andi
* 3/3  Store via 0(a3) before bumping a3 and enable c.sd patterns

Impact
------
* Code size: the __memcpy_noalignment object shrinks by ~7% on rv64gc builds.

* Performance (hardware only):
  Method: Based on glibc’s standard bench-memcpy (unmodified). We first modified 
  the original memcpy_noalignment implementation and duplicated the unmodified 
  version as memcpy_noalignment_original for baseline comparison. Each function 
  was benchmarked with warm-up followed by 100 runs, reporting geometric-mean 
  time ratios new/base (<1.0 indicates faster). 
  
  Platform: T-Head TH1520

  TH1520
    0–8B:      0.965  [0.9638, 0.9658]
    8–16B:     0.911  [0.9103, 0.9126]
    16–32B:    0.949  [0.9486, 0.9502]
    32–64B:    0.946  [0.9427, 0.9494]
    64–128B:   0.984  [0.9814, 0.9868]
    128–256B:  0.951  [0.9500, 0.9527]
    Overall:   0.9985 [0.9984, 0.9986]

Reproducibility
---------------
* Pinning: runs were CPU-pinned on real hardware. TH1520 was pinned to
  a dedicated core.
* Isolation: system load kept minimal; background services reduced as far
  as practical; CPU governor set to performance.
* Statistics: 95% CIs are reported above.

Thanks for reviewing.

Yao Zihong (3):
  riscv: memcpy_noalignment: Make register allocation Zca-friendly
  riscv: memcpy_noalignment: Fold SZREG/BLOCK_SIZE alignment to single
    andi
  riscv: memcpy_noalignment: Reorder to store via a3, then bump a3

 sysdeps/riscv/multiarch/memcpy_noalignment.S | 42 +++++++++-----------
 1 file changed, 19 insertions(+), 23 deletions(-)

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2.47.2