[PATCH 20/22] atomic: Consolidate atomic_write_barrier implementation

[Wilco Dijkstra]

Hi Adhemerval,
 
> All ABIs, except alpha and sparc, define it to
> atomic_full_barrier/__sync_synchronize, which can be mapped to
> __atomic_thread_fence (__ATOMIC_RELEASE).
>
> For alpha, it uses a 'wmb' which does not map to any of C11
> barriers.
>
> For sparc it uses a stronger 'member #LoadStore | #StoreStore',
> where the release barrier maps to just 'membar #StoreLoad'.  The
> patch keeps the sparc definition.
> 
> For PowerPC, it allows the use of lwsync for additional chips
> (since _ARCH_PWR4 does not cover all chips that support it).
>
> Tested on aarch64-linux-gnu.
>
> Co-authored-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>

LGTM.

Reviewed-by: Wilco Dijkstra  <Wilco.Dijkstra@arm.com>

Cheers,
Wilco