[PATCH 06/12] riscv/cfi: Add prctl definitions for RISC-V CFI

[Deepak Gupta]

On Wed, Jun 18, 2025 at 01:42:52AM -0700, Jesse Huang wrote:
>These operations are for setting/retrieving/locking the status of the
>landing pad and the shadow stack extensions.
>---
> .../unix/sysv/linux/riscv/include/asm/prctl.h | 48 +++++++++++++++++++
> 1 file changed, 48 insertions(+)
> create mode 100644 sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
>
>diff --git a/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h b/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
>new file mode 100644
>index 0000000000..790ba88a99
>--- /dev/null
>+++ b/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
>@@ -0,0 +1,48 @@
>+/*
>+ * Get the current shadow stack configuration for the current thread,
>+ * this will be the value configured via PR_SET_SHADOW_STACK_STATUS.
>+ */
>+#define PR_GET_SHADOW_STACK_STATUS	74
>+
>+/*
>+ * Set the current shadow stack configuration.  Enabling the shadow
>+ * stack will cause a shadow stack to be allocated for the thread.
>+ */
>+#define PR_SET_SHADOW_STACK_STATUS	75
>+# define PR_SHADOW_STACK_ENABLE		(1UL << 0)
>+# define PR_SHADOW_STACK_WRITE		(1UL << 1)
>+# define PR_SHADOW_STACK_PUSH		(1UL << 2)
>+
>+/*
>+ * Prevent further changes to the specified shadow stack
>+ * configuration.  All bits may be locked via this call, including
>+ * undefined bits.
>+ */
>+#define PR_LOCK_SHADOW_STACK_STATUS	76

Thanks to arm64 GCS patches, shadow stack one's are settled.

There are new prctls that got added, shifting landing pad prctls more down
in numbering.

They are 79, 80, 81 (if kernel patches rebased on 6.16)
I'll send out kernel patches rebased on 6.16-rc1.

>+/*
>+ * Get the current indirect branch tracking configuration for the current
>+ * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS.
>+ */
>+#define PR_GET_INDIR_BR_LP_STATUS	77
>+
>+/*
>+ * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE will
>+ * enable cpu feature for user thread, to track all indirect branches and ensure
>+ * they land on arch defined landing pad instruction.
>+ * x86 - If enabled, an indirect branch must land on `ENDBRANCH` instruction.
>+ * arch64 - If enabled, an indirect branch must land on `BTI` instruction.
>+ * riscv - If enabled, an indirect branch must land on `lpad` instruction.
>+ * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect
>+ * branches will no more be tracked by cpu to land on arch defined landing pad
>+ * instruction.
>+ */
>+#define PR_SET_INDIR_BR_LP_STATUS	78
>+# define PR_INDIR_BR_LP_ENABLE		(1UL << 0)
>+
>+/*
>+ * Prevent further changes to the specified indirect branch tracking
>+ * configuration.  All bits may be locked via this call, including
>+ * undefined bits.
>+ */
>+#define PR_LOCK_INDIR_BR_LP_STATUS	79
>-- 
>2.39.3
>