[PATCH v6 00/23] Handle ld.so with LOAD segment gaps in _dl_find_object (bug 31943)

[Wilco Dijkstra]

Hi Adhemerval,

> I think we will need some kernel support since this information depends
> of the internal hardware and use page size, AMD changed internally 
> the PTE Coalescing from 4 to 8 entries in Zen3. The ARM Contiguous bit
> also alignment require also depends of the page size used, where it is
> either 64k (4k page size) or 2M (16k, 64k).

Aligning mmap seems like a good idea - and choosing an alignment slightly
larger to cover typical coalescing sizes should be OK.

> I recall crossed a paper where they find that most advantages come from
> in fact superpages [1] ("In general, the improvements in unhalted clock 
> cycles offered by reservations and coalescing are modest, with superpages 
> tending to make a larger difference.) and that kernel allocating schemes
> seems to play a large hole (from the discussion of Linux vs FreeBSD
> allocation). 

Yes huge pages are always best. On modern kernels with folios THP looks really
good, so I'm thinking of enabling THP by default in malloc.

> So I am not sure if all the complexity of trickling down this information 
> to userspace will really pays off, for workloads that shows a lot of TLS 
> pressure it seems that largepages will be a better focus.

Having a few defines for these (including coalescing size and typical huge page
size) would be useful at least internally. It would help malloc and it might avoid
having to query the kernel for them at malloc startup.

Cheers,
Wilco