[PATCH] math: Order signed zeros in fmin and fmax.

[Wilco Dijkstra]

Hi Adhemerval,


> This is from writing fmin/fmax like this:
>
>   if (!isunordered (x, y))
>   {
>     if (__glibc_unlikely (x == y))
>       return signbit (x) ? x : y;
>     return x < y ? x : y;
>   }

Btw that should use isless (x, y) to save yet another instruction - on AArch64
I get this now:

0000000000000000 <__fmin>:
   0:	1e612000 	fcmp	d0, d1
   4:	54000086 	b.vs	14 <__fmin+0x14>
   8:	54000220 	b.eq	4c <__fmin+0x4c>  // b.none
   c:	1e605c20 	fcsel	d0, d1, d0, pl	// pl = nfrst
  10:	d65f03c0 	ret
  14:	1e62401f 	fcvt	s31, d0
  18:	52aff001 	mov	w1, #0x7f800000            	// #2139095040
  1c:	1e2603e0 	fmov	w0, s31
  20:	120a2000 	and	w0, w0, #0x7fc00000
  24:	6b01001f 	cmp	w0, w1
  28:	540001a0 	b.eq	5c <__fmin+0x5c>  // b.none
  2c:	1e62403f 	fcvt	s31, d1
  30:	1e2603e0 	fmov	w0, s31
  34:	120a2000 	and	w0, w0, #0x7fc00000
  38:	6b01001f 	cmp	w0, w1
  3c:	54000100 	b.eq	5c <__fmin+0x5c>  // b.none
  40:	1e612020 	fcmp	d1, d1
  44:	1e616c00 	fcsel	d0, d0, d1, vs
  48:	d65f03c0 	ret
  4c:	9e660000 	fmov	x0, d0
  50:	f100001f 	cmp	x0, #0x0
  54:	1e61bc00 	fcsel	d0, d0, d1, lt	// lt = tstop
  58:	d65f03c0 	ret
  5c:	1e612800 	fadd	d0, d0, d1
  60:	d65f03c0 	ret

I don't think any assembly code could ever beat that...

> We do have an inline implementation for __issignalingf on include/math.h
> and math/math.h already have a proper TG_MATH call to issignaling.  So
> I think should a matter to add a double variant and maybe a per-type
> one on some sysdeps/ieee754/type/header. 

Yes it's trivial to add a double variant (and we can improve the float version).
There are also issignaling(f)_inline functions which would become redundant
once issignaling inlines float/double cases in GLIBC. It's a shame GCC/LLVM are
still unable to both inline and generate correct code for any of these is* functions...

Cheers,
Wilco