[PATCH v2] aarch64: add optimised strspn/strcspn

[Wilco Dijkstra]

Hi remph,

> Does that mean keeping the .balign 16 before the second loop?  Without
> skipping half a cacheline at the beginning, that means the second loop will
> have 2 instructions over the next cacheline boundary.  Either it takes 4
> instruction fetches but fits in one cacheline, or it takes 3 fetches but 2
> cachelines.  Is it worth optimising for the instruction fetch at the expense
> of the cache?

You could try removing both balign's before the 2nd loop. That avoids the 2 NOPs,
and since the loop end is now aligned, it means 3 fetches and it fits in a cacheline.

The key thing to avoid is to use alignment directives that keep the loop misaligned
so that it requires 4 fetches. Fetching across cachelines does not add extra penalties.
Basically what matters the most is the instructions you execute, after that alignment
and fetching and finally keeping code compact to reduce I-cache misses.

Cheers,
Wilco