[PATCH v2] aarch64: add optimised strspn/strcspn

[lhr@disroot.org]

> +	.balign 64,,16
> 
> This doesn't seem to be very effective - this loop is at a bad alignment.
> We typically use .p2align 4 for performance critical loops. If you use the max
> padding feature, you always need a 2nd directive for minimum alignment
> (so you avoid getting no alignment at all if the padding would be too large).

I thought the only important thing was making the loop fit inside a single
cacheline?  My reasoning for the alignment directive is that the end of the
loop already falls before a 64B cacheline boundary, and padding it to 32B
would make it straddle 2 cachelines.  The directive is only there in case
the beginning of the loop gets closer to the 64B boundary.

> I think this could be done by using a mask to clear off bits from syndrome
> rather than a variable shift, and then setting the mask to zero for the next
> iteration. Then you don't ever need the extra ADD at the end.
> 
> Or even better, treat the first 16 bytes specially - then the shift works fine
> and you just return ctz (syndrome) >> 2. Plus it allows interleaving of the
> instructions, eg. moving the ldr q0, [s] much earlier. The first 16 bytes will
> be faster as you save at least 6 instructions, we remove 2 instructions from
> the loop and 2 in the tail.

I have implemented both of these and attached them (all the other recommendations
are implemented in both patches).  I favour the mask option, becuase when I
tested them that one got better and more consistent performance, and the
partially unrolled loop got inconsistent performance improvements and declines,
especially on the A72.  If this all checks out I'll resubmit it as v3.
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