[PATCH v13 7/7] riscv: Add and use alignment-ignorant memcpy

[Adhemerval Zanella Netto]

On 02/03/24 07:33, Andreas Schwab wrote:
> On Feb 27 2024, Evan Green wrote:
> 
>> For CPU implementations that can perform unaligned accesses with little
>> or no performance penalty, create a memcpy implementation that does not
>> bother aligning buffers. It will use a block of integer registers, a
>> single integer register, and fall back to bytewise copy for the
>> remainder.
> 
> How has that been tested?  It causes memory corruption.
> 

The memcpy optimization has multiple issues:

 1. The implementation is wrong: the chunk size calculation is wrong
 leading to invalid memory access.

 2. It adds ifunc supports as default, so --disable-multi-arch does
 not work as expected for riscv.

 3. It mixes Linux files (memcpy ifunc selection which requires the
 vDSO/syscall mechanism) with generic support (the memcpy
 optimization itself).

 4. There is no __libc_ifunc_impl_list, which makes testing only
 check the selected implementation instead of all supported
 by the system.

The 2., 3., and 4. are not really a problem since they came most likely
from code base inexperience. However, the 1. is *really* a red
flag since it means that you did not run a 'make check' to certify
no regressions were found.

I could trigger the same failures on qemu-system/qemu-user by forcing the 
implementation to be used as default, even if your hardware does have 
RISCV_HWPROBE_MISALIGNED_FAST, you could also check for correctness.

I sent a newer version that [1] should fix all the issues I have found. 
The C implementation is also easier to follow and it should generate 
code as good as the assembly version, so please check if on real 
hardware (I have only tested on qemu). As per the previous discussion,
I would like to use this as a base for a generic implementation; to 
avoid each architecture to reimplement the same code (as I did for some 
string implementations).

[1] https://patchwork.sourceware.org/project/glibc/patch/20240304175902.1479562-1-adhemerval.zanella@linaro.org/