[PATCH 3/3] x86: Set default non_temporal_threshold for Zhaoxin processors

[Mayshao-oc]

On Thu, Jun 27, 2024 at 2:10 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Thu, Jun 27, 2024 at 1:05 PM Mayshao-oc <Mayshao-oc@zhaoxin.com> wrote:
> >
> >
> > On Wen, Jun 26, 2024 at 11:29 AM  Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > >
> > > On Wed, Jun 26, 2024 at 10:47 AM MayShao <MayShao-oc@zhaoxin.com> wrote:
> > > >
> > > > From: MayShao <mayshao-oc@zhaoxin.com>
> > > >
> > > > Current 'non_temporal_threshold' set to 'non_temporal_threshold_lowbound'
> > > > on Zhaoxin processors without ERMS. The default
> > > > 'non_temporal_threshold_lowbound' is too small for the KH-40000 and KX-7000
> > > > Zhaoxin processors, this patch updates the value to
> > > > 'shared / cachesize_non_temporal_divisor'.
> > > > ---
> > > >  sysdeps/x86/cpu-features.c | 2 ++
> > > >  sysdeps/x86/dl-cacheinfo.h | 3 ++-
> > > >  2 files changed, 4 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> > > > index 24fbf699b9..55dac6a8b2 100644
> > > > --- a/sysdeps/x86/cpu-features.c
> > > > +++ b/sysdeps/x86/cpu-features.c
> > > > @@ -1060,7 +1060,9 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht
> > > >                  break;
> > > >
> > > >              case 0x5b:
> > > > +                cpu_features->cachesize_non_temporal_divisor = 2;
> > > >              case 0x6b:
> > > > +                cpu_features->cachesize_non_temporal_divisor = 4;
> > > >                  cpu_features->preferred[index_arch_AVX_Fast_Unaligned_Load]
> > > >                    &= ~bit_arch_AVX_Fast_Unaligned_Load;
> > > >
> > > > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
> > > > index 3a6ec4ef9f..438997a707 100644
> > > > --- a/sysdeps/x86/dl-cacheinfo.h
> > > > +++ b/sysdeps/x86/dl-cacheinfo.h
> > > > @@ -935,7 +935,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
> > > >       a higher risk of actually thrashing the cache as they don't have a HW LRU
> > > >       hint. As well, their performance in highly parallel situations is
> > > >       noticeably worse.  */
> > > > -  if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS))
> > > > +  if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS)
> > > > +       && cpu_features->basic.kind != arch_kind_zhaoxin)
> > >
> > > Can you update the comment to explain why zhaoxin is an exception.
> >
> > Yes, I will update it.  I am preparing to use the following comment:
> >
> > '''
> > /* If no ERMS, we use the per-thread L3 chunking. Normal cacheable stores run
> >      a higher risk of actually thrashing the cache as they don't have a HW LRU
> >      hint. As well, their performance in highly parallel situations is
> >      noticeably worse. Zhaoxin processor is an exception,  the lowbound is not
> >      suitable for them based on actual test data.  */
> > ""
> 
> Sure although "Zhaoxin processor is" -> "Zhaoxin processors are"

I will fix it.  Thanks.