[PATCH 3/3] x86: Set default non_temporal_threshold for Zhaoxin processors

[MayShao]

From: MayShao <mayshao-oc@zhaoxin.com>

Current 'non_temporal_threshold' set to 'non_temporal_threshold_lowbound'
on Zhaoxin processors without ERMS. The default
'non_temporal_threshold_lowbound' is too small for the KH-40000 and KX-7000
Zhaoxin processors, this patch updates the value to
'shared / cachesize_non_temporal_divisor'.
---
 sysdeps/x86/cpu-features.c | 2 ++
 sysdeps/x86/dl-cacheinfo.h | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 24fbf699b9..55dac6a8b2 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -1060,7 +1060,9 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht
                 break;
 
             case 0x5b:
+                cpu_features->cachesize_non_temporal_divisor = 2;
             case 0x6b:
+                cpu_features->cachesize_non_temporal_divisor = 4;
                 cpu_features->preferred[index_arch_AVX_Fast_Unaligned_Load]
                   &= ~bit_arch_AVX_Fast_Unaligned_Load;
 
diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
index 3a6ec4ef9f..438997a707 100644
--- a/sysdeps/x86/dl-cacheinfo.h
+++ b/sysdeps/x86/dl-cacheinfo.h
@@ -935,7 +935,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
      a higher risk of actually thrashing the cache as they don't have a HW LRU
      hint. As well, their performance in highly parallel situations is
      noticeably worse.  */
-  if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS))
+  if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS) 
+       && cpu_features->basic.kind != arch_kind_zhaoxin)
     non_temporal_threshold = non_temporal_threshold_lowbound;
   /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of
      'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best
-- 
2.34.1