[PATCH] RISC-V: Add support for dl_runtime_profile (BZ #31151)

[Aurelien Jarno]

On 2023-12-21 00:25, Aurelien Jarno wrote:
> On 2023-12-20 12:27, Palmer Dabbelt wrote:
> > On Fri, 15 Dec 2023 13:44:47 PST (-0800), aurelien@aurel32.net wrote:
> > > Code is mostly inspired from the LoongArch one, which has a similar ABI,
> > > with minor changes to support riscv32 and register differences.
> > >
> > > This fixes elf/tst-sprof-basic. This also fixes elf/tst-audit1,
> > > elf/tst-audit2 and elf/tst-audit8 with recent binutils snapshots when
> > > --enable-bind-now is used.
> > >
> > > Resolves: BZ #31151
> > > ---
> > >  sysdeps/riscv/Makefile        |   4 +
> > >  sysdeps/riscv/dl-link.sym     |  18 ++++
> > >  sysdeps/riscv/dl-machine.h    |  27 +++++-
> > >  sysdeps/riscv/dl-trampoline.S | 177 ++++++++++++++++++++++++++++++++++
> > >  4 files changed, 225 insertions(+), 1 deletion(-)
> > >  create mode 100644 sysdeps/riscv/dl-link.sym
> > >
> > > diff --git a/sysdeps/riscv/Makefile b/sysdeps/riscv/Makefile
> > > index 8fb10b164f..c08753ae8a 100644
> > > --- a/sysdeps/riscv/Makefile
> > > +++ b/sysdeps/riscv/Makefile
> > > @@ -2,6 +2,10 @@ ifeq ($(subdir),misc)
> > >  sysdep_headers += sys/asm.h
> > >  endif
> > >
> > > +ifeq ($(subdir),elf)
> > > +gen-as-const-headers += dl-link.sym
> > > +endif
> > > +
> > >  # RISC-V's assembler also needs to know about PIC as it changes the definition
> > >  # of some assembler macros.
> > >  ASFLAGS-.os += $(pic-ccflag)
> > > diff --git a/sysdeps/riscv/dl-link.sym b/sysdeps/riscv/dl-link.sym
> > > new file mode 100644
> > > index 0000000000..b430a064c9
> > > --- /dev/null
> > > +++ b/sysdeps/riscv/dl-link.sym
> > > @@ -0,0 +1,18 @@
> > > +#include <stddef.h>
> > > +#include <sysdep.h>
> > > +#include <link.h>
> > > +
> > > +DL_SIZEOF_RG            sizeof(struct La_riscv_regs)
> > > +DL_SIZEOF_RV            sizeof(struct La_riscv_retval)
> > > +
> > > +DL_OFFSET_RG_A0         offsetof(struct La_riscv_regs, lr_reg)
> > > +#ifndef __riscv_float_abi_soft
> > > +DL_OFFSET_RG_FA0        offsetof(struct La_riscv_regs, lr_fpreg)
> > > +#endif
> > > +DL_OFFSET_RG_RA         offsetof(struct La_riscv_regs, lr_ra)
> > > +DL_OFFSET_RG_SP         offsetof(struct La_riscv_regs, lr_sp)
> > > +
> > > +DL_OFFSET_RV_A0         offsetof(struct La_riscv_retval, lrv_a0)
> > > +#ifndef __riscv_float_abi_soft
> > > +DL_OFFSET_RV_FA0        offsetof(struct La_riscv_retval, lrv_fa0)
> > > +#endif
> > > diff --git a/sysdeps/riscv/dl-machine.h b/sysdeps/riscv/dl-machine.h
> > > index c0c9bd93ad..05bfa08da5 100644
> > > --- a/sysdeps/riscv/dl-machine.h
> > > +++ b/sysdeps/riscv/dl-machine.h
> > > @@ -313,13 +313,38 @@ elf_machine_runtime_setup (struct link_map *l, struct r_scope_elem *scope[],
> > >    if (l->l_info[DT_JMPREL])
> > >      {
> > >        extern void _dl_runtime_resolve (void) __attribute__ ((visibility ("hidden")));
> > > +      extern void _dl_runtime_profile (void) __attribute__ ((visibility ("hidden")));
> > >        ElfW(Addr) *gotplt = (ElfW(Addr) *) D_PTR (l, l_info[DT_PLTGOT]);
> > >        /* If a library is prelinked but we have to relocate anyway,
> > >  	 we have to be able to undo the prelinking of .got.plt.
> > >  	 The prelinker saved the address of .plt for us here.  */
> > >        if (gotplt[1])
> > >  	l->l_mach.plt = gotplt[1] + l->l_addr;
> > > -      gotplt[0] = (ElfW(Addr)) &_dl_runtime_resolve;
> > > +      /* The got[0] entry contains the address of a function which gets
> > 
> > At least "gotplt[0]", our names are different in here. 
> 
> Good catch, I fixed that locally.
> 
> > That makes this almost exactly the same as the aarch64 port, except the 
> > index (which is 2 there, as it is in most ports).  Presumably there's 
> > some ABI here, but I can't figure out why?
> 
> I don't know the reason, but from what I understand it matches the
> assembly code that binutils generates [1]. _dl_runtime_resolve is loaded
> directly from the .got.plt address (ie at index 0). For instance, on
> aarch64, it is loaded with an offset of 0x10, which corresponds to an
> index of 2.
> 
> [1] https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=bfd/elfnn-riscv.c;h=042266e791b453e7ef9b91153e29cc88e3f83a3f;hb=HEAD#l316

As pointed out by Andreas, this code from binutils matches the code from
the Procedure Linkage Table section of the RISC-V ABIs Specification. 

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                     http://aurel32.net