[PATCH] LoongArch: Add support for TLS Descriptors

[Xi Ruoyao]

On Wed, 2023-12-06 at 16:05 +0800, Xi Ruoyao wrote:
> On Wed, 2023-12-06 at 15:46 +0800, mengqinggang wrote:
> > For AArch64, FCMP and CSET similar to FCMP.CLT.D and MOVCF2GR.
> > ADD, STR and LDR can be inserted between FCMP and CSET.
> > But it seems that there is no BLR (similar to JIRL) inserted between
> > FCMP and CSET.
> > AARCH64 has no save and restore FPSR and FPCR in _dl_tlsdesc_dynamic
> > function.
> 
> AArch64 tlsdesc call pattern clobber CC registers:
> 
> (define_insn "tlsdesc_small_advsimd_<mode>"
>   [(set (reg:PTR R0_REGNUM)
>         (unspec:PTR [(match_operand 0 "aarch64_valid_symref" "S")]
>                     UNSPEC_TLSDESC))
>    (clobber (reg:DI LR_REGNUM))
>    (clobber (reg:CC CC_REGNUM)) # <=============== !!!!!!!!!!!!!
>    (clobber (match_scratch:DI 1 "=r"))
>    (use (reg:DI FP_REGNUM))]
>   "TARGET_TLS_DESC && !TARGET_SVE"
>   "adrp\\tx0, %A0\;ldr\\t%<w>1, [x0, #%L0]\;add\\t<w>0, <w>0, %L0\;.tlsdesccall\\t%0\;blr\\t%1"
>   [(set_attr "type" "call")
>    (set_attr "length" "16")])
> 
> So GCC won't insert it between FCMP and CSET.  If you want the same
> effect you need (clobber (reg:CC FCC_REG_FIRST)) (clobber (reg:CC
> FCC_REG_FIRST + 1)) ... ... (clobber (reg:CC FCC_REG_LAST)) as I've
> already suggested.

Correction: it should be reg:FCC instead of reg:CC, as we are using
FCCmode instead of CCmode of AArch64.

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University