[PATCH] LoongArch: Add support for TLS Descriptors

[mengqinggang]

在 2023/12/4 下午5:01, Xi Ruoyao 写道:
> On Mon, 2023-12-04 at 09:49 +0100, Florian Weimer wrote:
>> * Xi Ruoyao:
>>
>>> On Mon, 2023-12-04 at 09:13 +0100, Florian Weimer wrote:
>>>> * Xi Ruoyao:
>>>>
>>>>> I made up this:
>>>>>
>>>>> diff --git a/sysdeps/loongarch/Makefile b/sysdeps/loongarch/Makefile
>>>>> index 43d2f583cd..64c1ea1294 100644
>>>>> --- a/sysdeps/loongarch/Makefile
>>>>> +++ b/sysdeps/loongarch/Makefile
>>>>> @@ -15,3 +15,16 @@ ASFLAGS-.os += $(pic-ccflag)
>>>>>    ifeq (yes,$(have-cmodel-medium))
>>>>>    CFLAGS-.oS += -mcmodel=medium
>>>>>    endif
>>>>> +
>>>>> +# Make _dl_tlsdesc_dynamic slow path less expensive by denying __tls_get_addr
>>>>> +# from using any FPR.
>>>>> +#
>>>>> +# Attention: if you see an ICE here, it's likely __tls_get_addr is doing
>>>>> +# something wrong: why should it do floating-point operations anyway?!
>>>>> +# Please fix it instead of complain to GCC maintainers.
>>>>> +ifeq (yes,$(have-mno-lsx))
>>>>> +CFLAGS-libc-tls.c += -mno-lsx
>>>>> +endif
>>>> This is not correct: __tls_get_addr may call malloc, and an interposed
>>>> malloc is free to use the full register file.  You need to perform a
>>>> context switch here, similar to what the lazy binding trampoline does.
>>> Alright, but then do we need to save and restore fcsr and fcc as well?
>>> AFAIK they should be saved during a context switch, and AFAIK there are
>>> no rules saying "interposed malloc cannot alter floating-point execution
>>> environment".
>> Sorry, I'm not familiar with those register names and floating point
>> matters.
>>
>> That being said, I don't think malloc may change the rounding mode and
>> other floating point environment aspects.  Not sure about raising
>> exceptions, though.
> For example, for comparing some floating-point values and storing the
> result into a TLS variable, the compiler may generate something like
>
> fcmp.clt.d $fcc0, $f0, $f1
> pcalau12i $a0,%desc_pc_hi20(tls_sym)
> ld.d $a1,$a0,%desc_ld_pc_lo12(tls_sym)
> addi.d $a0,$a0,%desc_add_pc_lo12(tls_sym)
> jirl $ra,$a1,%desc_call(tls_sym)
> movcf2gr $t0,$fcc0
> st.d $t0,$a0,0

For AArch64, FCMP and CSET similar to FCMP.CLT.D and MOVCF2GR.
ADD, STR and LDR can be inserted between FCMP and CSET.
But it seems that there is no BLR (similar to JIRL) inserted between 
FCMP and CSET.
AARCH64 has no save and restore FPSR and FPCR in _dl_tlsdesc_dynamic 
function.

>
> Now if the interposed malloc clobbers fcc0 (well, it's simple: just
> compile the TU containing malloc with -fzero-call-used-regs=all), this
> sequence will blow up.
>
> So we need to either save and restore fcc registers here, or in the
> compiler add (clobber fcc0) (clobber fcc1) ... (clobber fcc7) for
> got_load_tls_desc.  Currently the draft GCC patch does not have these
> clobbers.
>
> (Note that this is not a problem with RISC-V because they use FPRs for
> outputs of floating-point comparisons and they don't have dedicated FCC
> registers).
>