[PATCH v2] x86: Add more feature definitions to isa-level.h

[H.J. Lu]

On Mon, Jun 27, 2022 at 7:42 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 7:39 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Mon, Jun 27, 2022 at 7:34 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > >
> > > On Mon, Jun 27, 2022 at 7:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> > > >
> > > > On Mon, Jun 27, 2022 at 7:03 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > > > >
> > > > > This commit doesn't change anything in itself.  It is just to add
> > > > > definitions that will be needed by future patches.
> > > > > ---
> > > > >  sysdeps/x86/isa-level.h | 10 ++++++++++
> > > > >  1 file changed, 10 insertions(+)
> > > > >
> > > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > > > index f293aea906..024d1deb80 100644
> > > > > --- a/sysdeps/x86/isa-level.h
> > > > > +++ b/sysdeps/x86/isa-level.h
> > > > > @@ -71,11 +71,13 @@
> > > > >  #define AVX512F_X86_ISA_LEVEL 4
> > > > >  #define AVX512VL_X86_ISA_LEVEL 4
> > > > >  #define AVX512BW_X86_ISA_LEVEL 4
> > > > > +#define AVX512DQ_X86_ISA_LEVEL 4
> > > > >
> > > > >  /* ISA level >= 3 guaranteed includes.  */
> > > > >  #define AVX_X86_ISA_LEVEL 3
> > > > >  #define AVX2_X86_ISA_LEVEL 3
> > > > >  #define BMI2_X86_ISA_LEVEL 3
> > > > > +#define MOVBE_X86_ISA_LEVEL 3
> > > > >
> > > > >  /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > > > >     for the following CPUs:
> > > > > @@ -89,6 +91,14 @@
> > > > >     when ISA level < 3.  */
> > > > >  #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > > > >
> > > > > +/* ISA level >= 2 guaranteed includes.  */
> > >
> > > Have a comment for ISA level 2 here.
> >
> > ISA is included.   But arch features can be enabled/disabled.
> >
> > > > > +#define SSE4_2_X86_ISA_LEVEL 2
> > > > > +#define SSSE3_X86_ISA_LEVEL 2
> > > > > +
> > > > > +/* NB: This feature is enabled when ISA level >= 2. No CPUs should be
> > > > > +   affected by this.  */
> > > >
> > > > /* Features enabled when ISA level >= 2.  */
> > >
> > > Hm? This is singular.
> >
> > Will more be added?
>
> None for this patchset. If in the future there are (with the same
> affected CPU set)
> I will make the comment plural.

Use singular then.

> >
> > >
> > > >
> > > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > > > > +
> > > > >  /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > > > >     macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > > > >     runtime checks.  They differ in two ways.
> > > > > --
> > > > > 2.34.1
> > > > >
> > > >
> > > >
> > > > --
> > > > H.J.
> >
> >
> >
> > --
> > H.J.



-- 
H.J.