[PATCH v9 4/4] elf: Fix runtime linker auditing on aarch64 (BZ #26643)

[Szabolcs Nagy]

The 01/11/2022 13:49, Adhemerval Zanella wrote:
> On 11/01/2022 08:16, Szabolcs Nagy wrote:
> > The 01/03/2022 10:25, Adhemerval Zanella via Libc-alpha wrote:
> >> @@ -142,13 +143,17 @@ _dl_runtime_profile:
> >>  	   Stack frame layout:
> >>  	   [sp,   #...] lr
> >>  	   [sp,   #...] &PLTGOT[n]
> >> -	   [sp,    #96] La_aarch64_regs
> >> -	   [sp,    #48] La_aarch64_retval
> >> -	   [sp,    #40] frame size return from pltenter
> >> -	   [sp,    #32] dl_profile_call saved x1
> >> -	   [sp,    #24] dl_profile_call saved x0
> >> -	   [sp,    #16] t1
> >> -	   [sp,     #0] x29, lr   <- x29
> >> +	   -----------------------
> >> +	   [sp,   #384] La_aarch64_regs::lr_xreg (x0-x8)
> >> +	   [sp,   #256] La_aarch64_regs::lr_vreg (q0-q7)
> >> +	   [sp,   #240] La_aarch64_regs::sp and La_aarch64_regs::lr
> >> +	   [sp,   #176] La_aarch64_retval::lrv_xreg (x0-x7)
> >> +	   [sp,   # 48] La_aarch64_retval::lrv_vreg (q0-q7)
> >> +	   [sp,   # 40] frame size return from pltenter
> >> +	   [sp,   # 32] dl_profile_call saved x1
> >> +	   [sp,   # 24] dl_profile_call saved x0
> >> +	   [sp,   # 16] t1
> >> +	   [sp,   #  0] x29, lr   <- x29
> >>  	 */
> > 
> > the layout in the comment looks backwards.
> 
> It follows the convention of the about layout:
> 
>         /* AArch64 we get called with:
>            ip0          &PLTGOT[2]
>            ip1          temp(dl resolver entry point)
>            [sp, #8]     lr
>            [sp, #0]     &PLTGOT[n]
> 	[...]
> 

i mean the order of the fields is wrong.

lr_xreg has larger address than lr_vreg
but in the struct it is the opposite.

i think you need to reorder the fields.
(but we don't have to document the exact offsets
here, so a simplified comment is fine too)