[PATCH] x86: Optimize atomic_compare_and_exchange_[val|bool]_acq [BZ #28537]

Oleh Derevenko oleh.derevenko@gmail.com
Thu Nov 4 11:42:01 GMT 2021


Hi Arjan,

On Wed, Nov 3, 2021 at 7:00 PM Arjan van de Ven <arjan@linux.intel.com> wrote:
> > Or if the value would cross a cache line boundary the plain read might
> > return half-updated value with the part from one cache line being new
> > and the other part being old.
>
> (I can't say in polite company what cmpxchg across cache lines does)

Well, the  "IA-32 Intel® Architecture Software Developer’s Manual,
Volume 3" in section 7.1.2.1 doesn't agree with you

The integrity of a bus lock is not affected by the alignment of the
memory field. The LOCK
semantics are followed for as many bus cycles as necessary to update
the entire operand.
However, it is recommend that locked accesses be aligned on their
natural boundaries for better
system performance:

-- 

Oleh Derevenko
-- Skype with underscore


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