[PATCH] x86: Optimize atomic_compare_and_exchange_[val|bool]_acq [BZ #28537]

[Florian Weimer]

* H. J. Lu:

>> Shouldn't GCC be fixed to generate the appropriate instruction sequence
>> for this architecture?  Should we perhaps switch to compiler atomics for
>> x86 instead of defining our own?
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103065
>
> In the meantime, we should help older compilers.

But wouldn't that extra read persist with fixed compilers, due to the
memory barrier?  So that there are two reads?

Maybe we need a hint flag for __atomic_compare_exchange_n, encoded in
the memory order?

Thanks,
Florian