[PATCH] x86: Optimize atomic_compare_and_exchange_[val|bool]_acq [BZ #28537]

[Florian Weimer]

* H. J. Lu via Libc-alpha:

> diff --git a/sysdeps/x86/atomic-machine.h b/sysdeps/x86/atomic-machine.h
> index 2692d94a92..92c7cf58b7 100644
> --- a/sysdeps/x86/atomic-machine.h
> +++ b/sysdeps/x86/atomic-machine.h
> @@ -73,9 +73,19 @@ typedef uintmax_t uatomic_max_t;
>  #define ATOMIC_EXCHANGE_USES_CAS	0
>  
>  #define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
> -  __sync_val_compare_and_swap (mem, oldval, newval)
> +  ({ __typeof (*(mem)) oldmem = *(mem), ret;				\
> +     ret = (oldmem == (oldval)						\
> +	    ? __sync_val_compare_and_swap (mem, oldval, newval)		\
> +	    : oldmem);							\
> +     ret; })
>  #define atomic_compare_and_exchange_bool_acq(mem, newval, oldval) \
> -  (! __sync_bool_compare_and_swap (mem, oldval, newval))
> +  ({ __typeof (*(mem)) old = *(mem);					\
> +     int ret;								\
> +     if (old != (oldval))						\
> +       ret = 1;								\
> +     else								\
> +       ret = !__sync_bool_compare_and_swap (mem, oldval, newval);	\
> +     ret; })

Shouldn't GCC be fixed to generate the appropriate instruction sequence
for this architecture?  Should we perhaps switch to compiler atomics for
x86 instead of defining our own?

Thanks,
Florian