[PATCH v2 3/3] powerpc64le: Add glibc-hwcaps support

[Segher Boessenkool]

Hi!

On Mon, Nov 16, 2020 at 11:51:27AM -0300, Tulio Magno Quites Machado Filho wrote:
> But then, we're back to this point you had raised:
> 
> > I think we need documentation what it means for a processor to implement
> > ISA 3.0, and not altivec.
> 
> Unfortunately, I think this documentation will only exist after a new -mcpu
> value is created.

Nothing that uses the vector registers can work, and disabling all
instructions that touch a vector register gets you 99.9% there.  This is
completely analoguous with -msoft-float (which really means "no FPRs").

With -mno-altivec you also have no VSCR and VRSAVE registers, just like
you lose FPSCR with -msoft-float.

But yes, this should be documented in the ABI, it matters for the
calling sequences etc.

A "normal" compilation may use the vector registers if the -mcpu= you
used allows that, so it cannot run on hardware without vector regs.  The
compiler can also use vector registers if you did not explicitly ask for
them (again analogous to the floating point registers), if you do not
explicitly forbid it of course.


Segher