[PATCH v2 10/18] RISC-V: Hard float support for 32-bit

[Maciej W. Rozycki]

On Sun, 12 Jul 2020, Alistair Francis wrote:

> >  I don't think there is a simple alternative available for RV32 that would
> > be worth keeping together with the RV64 variant.  Did I miss anything?
> > What instruction(s) do you have in mind?
> 
> Something like this for the generic RISC-V lround:
> 
> long int
> __lroundf (float x)
> {
> #if __WORDSIZE == 64
>   int64_t res;
>   asm ("fcvt.l.s %0, %1, rmm" : "=r" (res) : "f" (x));
> #else
>   int32_t res;
>   asm ("fcvt.w.s %0, %1, rmm" : "=r" (res) : "f" (x));
> #endif
>   return res;
> }
> 
> I'm not sure if it's clearer, but for some of the more complex
> functions (roundeven for example) it might be easier.
> 
> It also means if there is a bug fixed in one it'll end up fixed for both.

 Ah, you mean the `float' to `long int' conversion functions, necessarily 
ABI-specific due to the changing width of the latter data type.  Well, I 
meant the operations involving FCVT.L.D/FCVT.D.L.  I can see no RISC-V 
solution for them that would surpass the generic implementation.

 As far as your example above is concerned if we decided to merge the 
files at all, I would reduce it to:

#if __WORDSIZE == 64
# define OP "fcvt.l.s"
#elif __WORDSIZE == 32
# define OP "fcvt.w.s"
#else
# error Unsupported
#endif

long int
__lroundf (float x)
{
  long int res;
  asm (OP "\t%0, %1, rmm" : "=r" (res) : "f" (x));
  return res;
}

or suchlike (I'm not sure if there's any gain here from `res' having an 
explicit-width data type).  Likewise with the rest.

  Maciej