[PATCH v2 10/18] RISC-V: Hard float support for 32-bit

[Maciej W. Rozycki]

On Sat, 11 Jul 2020, Alistair Francis wrote:

> >  Shouldn't we also move the XLEN-agnostic optimised functions to
> > `sysdeps/riscv/rv{f,d}/' with this change?  I think we only need to keep
> > those that use the `long int' type at the interface in the XLEN-specific
> > directory.
> 
> They are all xlen dependent though. All of the 64-bit ones use
> fcvt.l.d (or something similar) which doesn't exist on RV32.

 Umm, right, I missed this detail, sorry for the confusion.

> Although the functions end up being the same, the actual assembly
> instruction called is different. We can look at consolidating them
> into a single file and do a xlen/__WORDSIZE macro check.

 I don't think there is a simple alternative available for RV32 that would 
be worth keeping together with the RV64 variant.  Did I miss anything?  
What instruction(s) do you have in mind?

> At this stage in glibc development I don't really want to change the
> floating point helpers. Can we leave this as is and then for the next
> release I can consolidate all of these into single files that do
> xlen/__WORDSIZE #ifdefs? That way we will just have a single file (for
> each operation) for RISC-V that will call a different assembly
> instruction based on xlen or __WORDSIZE.

 Sure, in these circumstances this change is fine with me then.

  Maciej