[PATCH V2 1/2] mips: add hp-timing support for MIPS R2

[Huang Pei]

On Fri, Dec 04, 2020 at 11:05:54AM +0000, Maciej W. Rozycki wrote:
> On Wed, 2 Dec 2020, Huang Pei wrote:
> 
> > MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be
> > enough for glibc.
> > 
> > DO remember Linux/MIPS added emulation for 'rdhwr %0, $2'，when disabled
> > or not supported, which would make the precision worse. If you got
> > unreasonable result, check your CPU Manual for whether your CPU
> > implemented it or not
> 
>  As discussed previously please rewrite the change description so as not 
> to mislead with irrelevant information.
> 
>   Maciej

What about this one?

......

MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be
enough for glibc.

"rhdwr/CP0 Hwena and kerel/hypervisor emulation" makes userspace CAN NOT
tell whether rdhwr is not enabled(AKA CP0 Hwena bit[2] is not set, so 
kernel/hypervisor emulated it) or not implemented but still emulated by
kernel/hypervisor, however, it DO "feel something is wrong with rdhwr" by
specific test(like computing the difference between the results of two
nearby rdhwr)

If you get unreasonable result, check your environment(CPU manual,
kernel, hypervisor)
......