[PATCH 1/3] mips: add hp-timing support for MIPS R2

[Maciej W. Rozycki]

On Mon, 30 Nov 2020, Adhemerval Zanella via Libc-alpha wrote:

> > MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be
> > enough for glibc.
> > 
> > DO remember Linux/MIPS added emulation for 'rdhwr %0, $2'，when disabled
> > or not supported, which would make the precision worse. If you got
> > unreasonable result, check your CPU Manual for whether your CPU
> > implemnted it or not
> 
> It seems that rdhwr trap simulation has been on kernel since 2.6.15-rc1
> (3c37026d43c47be), so it should be safe to assume current minimum kernel
> support for it.

 Nope, that was commit 1f5826bd0ed6c ("[MIPS] Added missing cases for 
rdhwr emulation") and Linux 2.6.25 respectively.  The other commit only 
added User Local Register (ULR) access emulation for TLS pointer access.

 Also CP0 Counter (CC) register access emulation relies on `read_c0_count',
which is NOT universally supported, as not all MIPS CPUs have the CC, in 
which case rubbish will be returned (the relevant instruction does not 
trap on invalid CP0 register accesses).

 None of this seems to matter however if we only handle this for R2 and 
higher ISA versions where both the CC and RDHWR are required by the 
architecture.

> However it does not only make the precision worse, but a missing rdwhr
> support would also slow down the loader since the hp-timing support is
> assumed to be 'fast' and loader code will use it regardless 
> LD_DEBUG=statistics is set or not.  It should be suffice to enabled it
> iff __mips_isa_rev is higher than 2, but do you know if there ARE chips
> which implement ISA higher than r2 that do not support this instruction?
> If so, how common are they?

 The RDHWR instruction is mandatory, though access to individual registers 
is controlled by the kernel, via the CP0 HWREna register bitmask.  We have 
had access enabled to registers 3:0 (CC is $2) unconditionally however:

	if (cpu_has_mips_r2_r6)
		hwrena |= MIPS_HWRENA_CPUNUM |
			  MIPS_HWRENA_SYNCISTEP |
			  MIPS_HWRENA_CC |
			  MIPS_HWRENA_CCRES;

ever since commit e01402b115cc ("More AP / SP bits for the 34K, the Malta 
bits and things."), that is Linux 2.6.15, and we can consider that a part 
of the Linux ABI.  Mentioning emulation in the context of R2 is therefore 
misleading in my opinion and the change description needs to be rewritten.

  Maciej