[PATCH] [powerpc] fenv_private.h clean up
Paul A. Clarke
pc@us.ibm.com
Sun Sep 8 18:53:00 GMT 2019
From: "Paul A. Clarke" <pc@us.ibm.com>
fenv_private.h includes unused functions, magic macro constants, and
some replicated common code fragments.
Remove unused functions, replace magic constants with constants from
fenv_libc.h, and refactor replicated code.
2019-09-08 Paul A. Clarke <pc@us.ibm.com>
* sysdeps/powerpc/fpu/fenv_private.h
(_FPU_ALL_TRAPS): Delete, replace with FPSCR_ENABLES_MASK.
(_FPU_MASK_RN): Delete.
(_FPU_MASK_NOT_RN_NI): Delete.
(_FPU_MASK_TRAPS_RN): Delete, replace with ~FPSCR_CONTROL_MASK.
(_FPU_MASK_FRAC_INEX_RET_CC): Delete, replace with ~FPSCR_STATUS_MASK.
(__TEST_AND_ENTER_NON_STOP): New.
(__TEST_AND_EXIT_NON_STOP): New.
(__libc_feholdbits_ppc): Delete, move code into
libc_feholdexcept_setround_ppc.
---
sysdeps/powerpc/fpu/fenv_private.h | 109 ++++++++++---------------------------
1 file changed, 29 insertions(+), 80 deletions(-)
diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h
index af72560..6072ad8 100644
--- a/sysdeps/powerpc/fpu/fenv_private.h
+++ b/sysdeps/powerpc/fpu/fenv_private.h
@@ -23,73 +23,40 @@
#include <fenv_libc.h>
#include <fpu_control.h>
-/* Mask for the exception enable bits. */
-#define _FPU_ALL_TRAPS (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM \
- | _FPU_MASK_XM | _FPU_MASK_IM)
+/* If the old env has no enabled exceptions and the new env has any enabled
+ exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
+ hardware into "precise mode" and may cause the FPU to run slower on some
+ hardware. */
+#define __TEST_AND_ENTER_NON_STOP(old, new) \
+ do { \
+ if ((old & FPSCR_ENABLES_MASK) == 0 && (new & FPSCR_ENABLES_MASK) != 0) \
+ (void) __fe_nomask_env_priv (); \
+ } while (0)
-/* Mask the rounding mode bits. */
-#define _FPU_MASK_RN 0xfffffffffffffffcLL
-
-/* Mask everything but the rounding modes and non-IEEE arithmetic flags. */
-#define _FPU_MASK_NOT_RN_NI 0xffffffff00000807LL
-
-/* Mask restore rounding mode and exception enabled. */
-#define _FPU_MASK_TRAPS_RN 0xffffffffffffff00LL
-
-/* Mask FP result flags, preserve fraction rounded/inexact bits. */
-#define _FPU_MASK_FRAC_INEX_RET_CC 0xfffffffffff80fffLL
+ /* If the old env had any enabled exceptions and the new env has no enabled
+ exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
+ FPU to run faster because it always takes the default action and can not
+ generate SIGFPE. */
+#define __TEST_AND_EXIT_NON_STOP(old, new) \
+ do { \
+ if ((old & FPSCR_ENABLES_MASK) != 0 && (new & FPSCR_ENABLES_MASK) == 0) \
+ (void) __fe_mask_env (); \
+ } while (0)
static __always_inline void
-__libc_feholdbits_ppc (fenv_t *envp, unsigned long long mask,
- unsigned long long bits)
+libc_feholdexcept_setround_ppc (fenv_t *envp, int r)
{
fenv_union_t old, new;
old.fenv = *envp = fegetenv_register ();
- new.l = (old.l & mask) | bits;
-
- /* If the old env had any enabled exceptions, then mask SIGFPE in the
- MSR FE0/FE1 bits. This may allow the FPU to run faster because it
- always takes the default action and can not generate SIGFPE. */
- if ((old.l & _FPU_ALL_TRAPS) != 0)
- (void) __fe_mask_env ();
+ __TEST_AND_ENTER_NON_STOP (old.l, 0);
+ /* Clear everything and set the rounding mode. */
+ new.l = r;
fesetenv_register (new.fenv);
}
-static __always_inline void
-libc_feholdexcept_ppc (fenv_t *envp)
-{
- __libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI, 0LL);
-}
-
-static __always_inline void
-libc_feholdexcept_setround_ppc (fenv_t *envp, int r)
-{
- __libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI & _FPU_MASK_RN, r);
-}
-
-static __always_inline void
-libc_fesetround_ppc (int r)
-{
- __fesetround_inline (r);
-}
-
-static __always_inline int
-libc_fetestexcept_ppc (int e)
-{
- fenv_union_t u;
- u.fenv = fegetenv_register ();
- return u.l & e;
-}
-
-static __always_inline void
-libc_feholdsetround_ppc (fenv_t *e, int r)
-{
- __libc_feholdbits_ppc (e, _FPU_MASK_TRAPS_RN, r);
-}
-
static __always_inline unsigned long long
__libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask,
unsigned long long new_mask)
@@ -102,19 +69,8 @@ __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask,
/* Merge bits while masking unwanted bits from new and old env. */
new.l = (old.l & old_mask) | (new.l & new_mask);
- /* If the old env has no enabled exceptions and the new env has any enabled
- exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
- hardware into "precise mode" and may cause the FPU to run slower on some
- hardware. */
- if ((old.l & _FPU_ALL_TRAPS) == 0 && (new.l & _FPU_ALL_TRAPS) != 0)
- (void) __fe_nomask_env_priv ();
-
- /* If the old env had any enabled exceptions and the new env has no enabled
- exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
- FPU to run faster because it always takes the default action and can not
- generate SIGFPE. */
- if ((old.l & _FPU_ALL_TRAPS) != 0 && (new.l & _FPU_ALL_TRAPS) == 0)
- (void) __fe_mask_env ();
+ __TEST_AND_EXIT_NON_STOP (old.l, new.l);
+ __TEST_AND_ENTER_NON_STOP (old.l, new.l);
/* If requesting to keep status, replace control, and merge exceptions,
and exceptions haven't changed, we can just set new control instead
@@ -146,12 +102,7 @@ libc_feresetround_ppc (fenv_t *envp)
{
fenv_union_t new = { .fenv = *envp };
- /* If the old env has no enabled exceptions and the new env has any enabled
- exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
- hardware into "precise mode" and may cause the FPU to run slower on some
- hardware. */
- if ((new.l & _FPU_ALL_TRAPS) != 0)
- (void) __fe_nomask_env_priv ();
+ __TEST_AND_EXIT_NON_STOP (0, new.l);
/* Atomically enable and raise (if appropriate) exceptions set in `new'. */
fesetenv_mode (new.fenv);
@@ -160,8 +111,8 @@ libc_feresetround_ppc (fenv_t *envp)
static __always_inline int
libc_feupdateenv_test_ppc (fenv_t *envp, int ex)
{
- return __libc_femergeenv_ppc (envp, _FPU_MASK_TRAPS_RN,
- _FPU_MASK_FRAC_INEX_RET_CC) & ex;
+ return __libc_femergeenv_ppc (envp, ~FPSCR_CONTROL_MASK,
+ ~FPSCR_STATUS_MASK) & ex;
}
static __always_inline void
@@ -205,8 +156,7 @@ libc_feholdsetround_ppc_ctx (struct rm_ctx *ctx, int r)
ctx->env = old.fenv;
if (__glibc_unlikely (new.l != old.l))
{
- if ((old.l & _FPU_ALL_TRAPS) != 0)
- (void) __fe_mask_env ();
+ __TEST_AND_ENTER_NON_STOP (old.l, 0);
fesetenv_mode (new.fenv);
ctx->updated_status = true;
}
@@ -226,8 +176,7 @@ libc_feholdsetround_noex_ppc_ctx (struct rm_ctx *ctx, int r)
ctx->env = old.fenv;
if (__glibc_unlikely (new.l != old.l))
{
- if ((old.l & _FPU_ALL_TRAPS) != 0)
- (void) __fe_mask_env ();
+ __TEST_AND_ENTER_NON_STOP (old.l, 0);
fesetenv_register (new.fenv);
ctx->updated_status = true;
}
--
1.8.3.1
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