[PATCH 3/4] [powerpc] fesetenv: optimize FPSCR access

Paul Clarke pc@us.ibm.com
Thu Aug 22 16:55:00 GMT 2019


On 8/21/19 5:13 PM, Paul E Murphy wrote:
> On 8/20/19 4:19 PM, Paul A. Clarke wrote:

>> diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c
>> index 009a4f0..5ca15c7 100644
>> --- a/sysdeps/powerpc/fpu/fesetenv.c
>> +++ b/sysdeps/powerpc/fpu/fesetenv.c
>> @@ -28,25 +26,23 @@ __fesetenv (const fenv_t *envp)

>>       /* If the old env has no enabled exceptions and the new env has any enabled
>>        exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put the
>>        hardware into "precise mode" and may cause the FPU to run slower on some
>>        hardware.  */
>> -  if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
>> +  if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0)
>>       (void) __fe_nomask_env_priv (); >
>>     /* If the old env had any enabled exceptions and the new env has no enabled
>>        exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
>>        FPU to run faster because it always takes the default action and can not
>>        generate SIGFPE. */
>> -  if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
>> +  if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0)
>>       (void)__fe_mask_env ();

> If you need to make another similar change, I might recommend consolidating the code to toggle the MSR bits.

Could you elaborate on what consolidation you are anticipating?

PC



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