[PATCH][AArch64] Adjust writeback in non-zero memset

[Siddhesh Poyarekar]

On 16/11/18 10:34 PM, Wilco Dijkstra wrote:
> I ran it on Cortex-A72, and there isn't a performance difference on the memset bench
> beyond measurement errors. On any out-of-order core address increments are
> executed in parallel with loads/stores, ie. they have no measurable latency and so
> their exact placement is irrelevant.

Thanks for the confirmation.  Looks OK to me.

Siddhesh