[PATCH 1/3] Guess L1 cache linesize for aarch64

[Siddhesh Poyarekar]

On Tuesday 10 October 2017 07:50 PM, Richard Henderson wrote:
>> maybe
> 
> Have you ever seen a system for which this was not true?
> I don't believe I have.

The Qualcomm Falkor chip shows the L2 dcache line size here instead of L1.

> They expect them to be exactly what they say they are.
> The question is, what do they expect to be able to do with that information.
> 
> Speaking for myself, I expect to be able to dynamically align objects on this
> linesize and for that to have some predictable effect on performance.

This should continue to work well even for falkor.  In fact, if a core
does this (i.e. deviate from L1 line size in ctr_el0) and also not
perform better (or at least not regress) then the designers should
understand that such a design would be sub-optimal.

Siddhesh