[PATCH 1/3] Guess L1 cache linesize for aarch64

[Siddhesh Poyarekar]

On Tuesday 10 October 2017 03:49 PM, Szabolcs Nagy wrote:
> On 08/06/17 23:57, Richard Henderson wrote:
>> +  /* Unfortunately, the registers that contain the actual cache info
>> +     (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux
>> +     kernel (though they need not have been).  However, CTR_EL0 contains
>> +     the *minimum* linesize in the entire cache hierarchy, and is
>> +     accessible to userland, for use in __aarch64_sync_cache_range,
>> +     and it is a reasonable assumption that the L1 cache will have that
>> +     minimum line size.  */
> 
> maybe

Right, but that's an architectural detail that may not be relevant for
sysconf.  That is, the assumption may be suitable for the way the
sysconf is typically used.

>> +    case _SC_LEVEL1_ICACHE_LINESIZE:
>> +    case _SC_LEVEL1_DCACHE_LINESIZE:
> 
> i can't find documentation for these, what meaning do users expect?

Applications may use these hints to try and align their code/data
suitably or read/write data in an optimal manner.  It needs to be
documented and I hope to have a patch ready for it soon, but I wanted to
be sure that this patch was in place since otherwise the documentation
does not make sense.

Siddhesh