Synchronizing auxiliary mutex data

[Andreas Schwab]

On Jun 21 2017, Alexander Monakov <amonakov@ispras.ru> wrote:

> Cache coherency protocol ensures that when another CPU prepares to write to
> memory, we lose posession of a copy of about-to-be-overwritten data in our cache.

Thanks, so any failure to see the right value must be something else.

Andreas.

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
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